Ihirangi huna
1 Xilinx DDR2 MIG 7 Aratohu Whakatau Mahinga
2 Kupu Whakataki
3 Whakawhanui Whanui
4 MIG Design Generation
5 Mahinga Whakamutunga RTL whakarerekētanga
6 Whakataurite i te Kaihanga Whakawhiti Mahi
7 Nga huarahi whaanui hei whakapai ake i te mahinga
8 Nga wa mahara ki runga
9 Nga Kaipupuri Kaiwhakahaere
10 Tohutoro
11 Tohutoro
12 Whakairinga Paanga

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Xilinx DDR2 MIG 7 Aratohu Whakatau Mahinga

Xilinx_DDR2_MIG_7_Mahinga-Whakatau-hua

Tuhipoka Nui: Ko tenei PDF ka taea te tango mai i te Rekoata Whakautu ka tukuna hei whakarei ake i tona whakamahinga me te panui. He mea nui kia mahara ko nga Rekoata Whakautu Web-i runga i nga ihirangi e whakahoutia ana i te wa e waatea ana nga korero hou. Kei te whakamahara koe ki te toro ki te Tautoko Hangarau Xilinx Webpae me te review (Xilinx Whakautu 63234) mo te putanga hou o tenei Whakautu.

Kupu Whakataki

Na te ahua o te hanga o nga maharatanga DDR2 me DDR3 me te hoahoa o te raupapa MIG 7, kaore i te tika te mahi.
Me mohio koe ki nga momo tawhā Jedec Timing me te Kaiwhakahaere Architecture, ka hiahia koe ki te whakahaere whaihanga ki te tiki i nga whakatau tata.
He rite tonu te maapono whanui mo te whakatau mahi engari he huarahi ngawari tenei tuhinga ki te whai hua ma te whakamahi i te MIG exampte hoahoa me te awhina o te papa whakamatautau me te whakaongaonga files piri ki konei.

Whakawhanui Whanui

Ko te pahi raraunga DRAM ka eke ki te paanui tata-te tihi anake i te wa e pakaru ana te panui me te tuhi, ka whakahekehia te reeti raraunga whai hua.
He torutoru exampKo nga utu o runga ko:

  • te wa i mua i te utu ki te uru ki nga rarangi i te peeke kotahi (Kaore te wahitau uru i roto i te rarangi haupae-pae kotahi)
  • tuhia te wa whakaora ki te huri mai i te tuhi ki te uru ki te panui
  • te wa huri pahi ki te huri mai i te panui ki te uru tuhituhi

Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-28
Aratuku Whaihua = Peak Bandwidth * He kaha 

MIG Design Generation

Tirohia te UG586 Upoko 1 mo nga taipitopito taahiraa-i-taahiraa mo te MIG IP me te exampte whakatipuranga hoahoa.
I mua i te whakahaere MIG 7 Series whaihanga mahi, mahia nga mea e whai ake nei kia pai ai to taiao whaihanga. Whakatuwheratia te MIG exampte hoahoa me te mahere i nga whare pukapuka e tika ana, whakahaere i te whaihanga, me te whakarite kia kite koe i te panui "kua paahitia te whakamatautau" i roto i te tuhinga.
Hei whakaatu i te rere kua hangaia e ahau he MIG IP mo xc7vx690tffg1761-2 me te tono i te examphoahoa.
E rua nga mea e tika ana kia mahara ko nga moka wahitau mahara me te kowhiringa mahere wahitau mahara.
Mo te exampNa, kua tohua e ahau te MT41J128M8XX-125 i raro i te waahanga mahara ki raro nga whiringa.Xilinx DDR2 MIG-7-Mahi-Whakatau-piki-1

Mo te wahanga mahara kua tohua mai i te Whakaahua-1, rarangi = 14, pou = 10 me te peeke = 3, no reira app_addr_width = rarangi + pou + peeke + rangatira = 28 Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-2

Ka taea e koe te kowhiri i te BANK_ROW_COLUMN, te ROW BANK Column ranei.
Kua mahue ahau i te Tiwae ROW BANK ko te mapi wahitau taunoa.

Exampte hoahoa Whakatairanga me te pae whakamatautau synthesizable

I raro i nga tautuhinga whaihanga, tohua QuestaSim/ModelSim Simulator ka tirotiro ki te waahi o nga whare pukapuka kua whakahiato.
Mo nga taipitopito mo te tohu ki te huarahi whakauru taputapu tuatoru, te kowhiri i te simulator whaainga, me te whakahiato me te mapi i nga whare pukapuka, ka taea e koe te titiro ki (UG900) Vivado Design Suite Aratohu Kaiwhakamahi Logic SimulationXilinx DDR2 MIG 7 Whakatau Mahinga-fig-3

Whakahaerehia te whaihanga i roto i te GUI (Pāwhiritia te Run Simulation Ripa i roto i te kaiwhakahaere kaupapa) me te mohio kei te kite koe i te karere "whakamatautau" i roto i te tuhinga.

Mahinga Whakamutunga RTL whakarerekētanga

  1. Pāwhiri-matau i te ripa puna, tohua "taapirihia, waihangahia ranei nga punaa whaihanga", ka tirotiro ki te mig7_perfsim_traffic_generator.sv file ka paato i te mutu hei taapiri.
  2. Pāwhiri-matau i te ripa puna, tohua "taapirihia, waihangahia nga punawai whaihanga", tirotiro ki te perfsim_stimulus.txt, ka paato i te whakaoti hei taapiri.
  3. Korerohia te example_top instantiation i roto i te sim_tb_top.v file.
  4. Tāpirihia nga rarangi RTL o raro ki sim_tb_top,v
  • localparam APP_ADDR_WIDTH = 28;
  • localparam APP_DATA_WIDTH = 64;
  • localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
  • localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
  • localparam BANK_WIDTH = 3;
  • localparam RANK_WIDTH = 1;
  • waea [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
  • waea [2:0] c0_ddr3_app_cmd;
  • waea c0_ddr3_app_en;
  • waea [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
  • waea c0_ddr3_app_wdf_end;
  • waea [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
  • waea c0_ddr3_app_wdf_wren;
  • waea [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
  • waea c0_ddr3_app_rd_data_end;
  • waea c0_ddr3_app_rd_data_valid;
  • waea c0_ddr3_app_rdy;
  • waea c0_ddr3_app_wdf_rdy;
  • waea c0_data_compare_error;
  • waea ui_clk;
  • waea ui_clk_sync_rst;
  • waea app_sr_req = 0;
  • waea app_ref_req = 0;
  • waea app_zq_req =0;
  • waea c0_app_wdf_mask =0;

FPGA Pūwhakahaere mahara tonu

mig_7series_0_mig u_mig_7series_0_mig (
// Tauranga atanga mahara

  • .ddr3_addr (ddr3_addr_fpga),
  • .ddr3_ba (ddr3_ba_fpga),
  • .ddr3_cas_n (ddr3_cas_n_fpga),
  • .ddr3_ck_n (ddr3_ck_n_fpga),
  • .ddr3_ck_p (ddr3_ck_p_fpga),
  • .ddr3_cke (ddr3_cke_fpga),
  • .ddr3_ras_n (ddr3_ras_n_fpga),
  • .ddr3_reset_n (ddr3_reset_n),
  • .ddr3_we_n (ddr3_we_n_fpga),
  • .ddr3_dq (ddr3_dq_fpga),
  • .ddr3_dqs_n (ddr3_dqs_n_fpga),
  • .ddr3_dqs_p (ddr3_dqs_p_fpga),
  • .init_calib_complete (init_calib_complete),
  • .ddr3_cs_n (ddr3_cs_n_fpga),
  • .ddr3_dm (ddr3_dm_fpga),
  • .ddr3_odt (ddr3_odt_fpga),

// Tauranga atanga tono

  • .app_addr (c0_ddr3_app_addr),
  • .app_cmd (c0_ddr3_app_cmd),
  • .app_en (c0_ddr3_app_en),
  • .app_wdf_data (c0_ddr3_app_wdf_data),
  • .app_wdf_end (c0_ddr3_app_wdf_end),
  • .app_wdf_wren (c0_ddr3_app_wdf_wren),
  • .app_rd_data (c0_ddr3_app_rd_data),
  • .app_rd_data_end (app_rd_data_end),
  • .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
  • .app_rdy (c0_ddr3_app_rdy),
  • .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
  • .app_sr_req (app_sr_req),
  • .app_ref_req (app_ref_req),
  • .app_zq_req (app_zq_req),
  • .app_sr_active (app_sr_active),
  • .app_ref_ack (app_ref_ack),
  • .app_zq_ack (app_zq_ack),
  • .ui_clk (ui_clk),
  • .ui_clk_sync_rst (ui_clk_sync_rst),
  • .app_wdf_mask (c0_ddr3_app_wdf_mask),

// Tauranga Karaka Pūnaha

  • .sys_clk_i (sys_clk_i),

// Tauranga Karaka Tohutoro

  • .clk_ref_i (clk_ref_i),
  • .sys_rst (sys_rst)
  • );

Mahinga waka generator instantiation

mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK ),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

u_traffic_gen
(
.clk (ui_clk ),
.tuatahi (ui_clk_sync_rst ),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy ),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data ),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd ),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

  • 5. Whakakē APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH me BANK_WIDTH kia rite ki to whiringa waahanga mahara.
    Ka taea te whiwhi uara mai i te _mig.v file.
  • Ko te ingoa inamata kua tohua he kowhai mig_7series_0_mig ka rereke pea i runga i to ingoa waahanga i te wa o te waihanga IP, manatoko mena kua tohua e koe he ingoa rereke ka huri kia rite.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-4
  • Kia hangahia te IP whakatuwheratia te _mig.v file me te tirotiro whakawhiti mo nga rereketanga o nga ingoa tohu LHS me te whakatika.
  • app_sr_req, app_ref_req me app_zq_req me arawhiti ki te 0.
  • Hei exampHe korero hou a le_top.v files ka taapirihia, ka kite pea koe "?" i te taha o te
    mig_7series_0_mig.v file i raro i nga puna whaihanga.
    Hei mapi i te tika file, pawhiria matau mig_7series_0_mig.v, tohua "Taapirihia nga Puna", Tirotiro ki
    /mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
    ka taapirihia te mig_7series_0_mig_sim.v file.
  • Mena ka kite koe "?" mo te mea kei raro files, tāpiri RTL katoa filekei roto i te karaka, kaiwhakahaere, ip_top,phy me nga kōpaki UI.
  • Kia oti nga huringa RTL me nga mea katoa e hiahiatia ana files ka taapirihia ki o Puna Whakaakoranga, Me rite te Arataki ki te Whakaahua 5.
    Ko te fileKo nga mea kua tohua ki te whero he taapiri hou, me te "?" Kei te tumanakohia i runga i nga waahanga ECC na te mea kua monoa te whiringa ECC i te whirihoranga mahara kua tohua.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-5

Whakatairanga File Whakaahuatanga
Ko ia tauira whakaohooho he 48 moka ka whakaahuahia te whakatakotoranga i nga Whakaahua 6-1 ki te 6-4.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-6

Whakawaehere Wāhitau (Wāhitau [35:0])

Kei te whakawaeheretia te wahitau i roto i te whakaohooho pera i te Whakaahua 7-1 ki te Whakaahua 7-6. Ko nga waahi waahi katoa me whakauru ki te whakatakotoranga hexadecimal. Ko nga waahi waahi katoa he whanui ka wehea ki te wha hei whakauru ki te whakatakotoranga hautekauono. Ka tukuna noa e te papa whakamatautau nga moka e hiahiatia ana o te mara wahitau ki te Kaiwhakahaere Mahara.
Mo te exampNa, i roto i te whirihoranga peeke e waru, ko nga Paraka peeke anake [2:0] ka tukuna ki te Kaiwhakahaere Mahara, ka warewarehia nga toenga moka. Ko nga moka taapiri mo tetahi mara wahitau ka tukuna hei whakauru i te wahitau i roto i te whakatakotoranga hexadecimal.
Me whakaū koe i te uara i whakauruhia kia rite ki te whanui o tetahi whirihoranga.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-7

  • Wāhitau Tīwae (Tīwae[11:0]) – Ko te Wāhitau Tīwae i roto i te whakaihiihi ka tukuna ki te 12 moka morahi, engari me whakatika e koe i runga i te tawhā whanui o te pou kua whakaritea i to hoahoa.
  • Wāhitau Haupae (Rarangi[15:0]) – Ko te wahitau haupae i roto i te whakaihiihi ka tukuna ki te 16 moka morahi, engari me whakatika e koe i runga i te tawhā whanui haupae kua whakaritea i to hoahoa.
  • Wāhitau Peeke (Peeke[3:0]) – Ko te wahitau peeke i roto i te whakaongaonga ka tukuna ki te morahi o nga moka e wha, engari me whakatika e koe tenei i runga i te tawhā whanui peeke kua whakaritea i to hoahoa.
  • Wāhitau Whakatau (Rarangi[3:0]) – Ko te wahitau rangatira i roto i te whakaihiihi ka tukuna ki te moka rawa e wha moka, engari me whakatika e koe tenei i runga i te tawhā whanui taumata kua whakaritea i to hoahoa.
    Ka whakaemihia te wahitau i runga i te tawhā MEM_ADDR_ORDER taumata-runga ka tukuna ki te atanga kaiwhakamahi

Whakahaua Tukua (Tuarua Tonoa [7:0])
Ko te tatau tukurua whakahau ko te maha o nga wa ka tukuna ano te whakahau ki te Atanga Kaiwhakamahi. Ko te wahitau mo ia tukurua ka piki ake ki te 8. Ko te morahi o te tatau tukurua he 128.
Karekau te pae whakamatautau e tirotiro i te rohe o te pou, ka takai ki te eke ki te tepe teitei o te pou i roto i nga pikinga.
Ko nga whakahau 128 ka whakakiia te wharangi. Mo tetahi wahitau tīwae i tua atu i te 0, ko te kaute tukurua o te 128 ka mutu te whakawhiti i te rohe o te pou me te takai ki te timatanga o te wahitau pou.

Te Whakamahinga Pahi
Ka tatauhia te whakamahi pahi ki te Atanga Kaiwhakamahi ma te whakaaro ki te maha o nga Panui me te Tuhi ka whakamahia te wharite e whai ake nei:

Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-8

  • E wha nga huringa karaka mahara a BL8
  • Ko te end_of_stimulus te wa ka oti nga whakahau katoa.
  • Ko te calib_done te wa ka oti te whakatikatika.

Example Tauira
Ko enei exampKo nga mea kei runga i te MEM_ADDR_ORDER kua tautuhia ki BANK_ROW_COLUMN.

Tauira Panui Kotahi
00_0_2_000F_00A_1 – He panui kotahi tenei tauira mai i te rarangi 10, rarangi 15, me te peeke tuarua.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-9Tauira Tuhituhi Takitahi
00_0_1_0040_010_0 – He tuhi kotahi tenei tauira ki te rarangi 32, rarangi 128, me te peeke tuatahi.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-10Tuhituhi me te Panui ki te Wāhitau Kotahi
00_0_2_000F_00A_0 – Ko tenei tauira he tuhi kotahi ki te rarangi 10, rarangi 15, me te peeke tuarua.
00_0_2_000F_00A_1 – He panui kotahi tenei tauira mai i te rarangi 10, rarangi 15, me te peeke tuaruaXilinx DDR2 MIG 7 Whakatau Mahinga-fig-11

He maha nga Tuhi me nga Panui me te Wāhitau Ōrite
0A_0_0_0010_000_0 – He rite tenei ki nga tuhi 10 me te waahi noho mai i te 0 ki te 80 ka kitea i te pou.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-12

0A_0_0_0010_000_1 – He rite tenei ki nga panui 10 me te waahi noho mai i te 0 ki te 80 ka kitea i te pou.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-13

Wrap Wharangi I te Tuhituhi
0A_0_2_000F_3F8_0 – He rite tenei ki nga tuhi 10 me te wahitau pou i takai ki te timatanga o te wharangi i muri i te tuhi kotahi.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-14

Whakataurite i te Kaihanga Whakawhiti Mahi

I tenei wa kua oti koe me MIG exampte whaihanga hoahoa. Ko te tikanga tenei kua reri to whakatauhanga whaihanga, kua mahia e koe nga whakarereketanga RTL whaihanga mahi, he tika te hierarchy whaihanga hou, kua mohio koe ki nga tauira whakaohooho. Whakahaerehia ano te whaihanga me te 16 nga tuhi me te panui i te perfsim_stimulus.txt.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-15

Me oma-katoa, tatari kia puta te tohu init_calib_complete, ka kite koe i te maha o nga tuhi me nga panui. Ka mutu te whaihanga. Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-16

Ka aakihia koe ki te whakamutu i te whaihanga, tohua Kao ka haere ki te matapihi tuhinga ka taea e koe te kite i nga tatauranga mahi. Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-17

Mena ka tohua e koe "whakamutua te whaihanga" ka tuhia nga tatauranga mahi ki a file whakaingoatia mig_band_width_output.txt kei roto i te sim_1/behave kōpaki.

Exampte ara whaiaronga:-
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behavXilinx DDR2 MIG 7 Whakatau Mahinga-fig-18

Ka miharo pea koe he aha te ōrautagKo te whakamahi pahi he ony 29. Whakahokia ano te whaihanga me nga tautuhinga IP kotahi engari ka huri noa i te whakaohooho file ki te 256 te tuhi me te 256 te panui

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Ka kite koe i te ōrautage rite 85, e kii ana ko te DDR3 he pai ake te whakamahi pahi mo te raupapa roa o te tuhi me te panui panui. Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-19

Nga huarahi whaanui hei whakapai ake i te mahinga

Ko nga mea e pa ana ki te whai hua ka wehewehea kia rua nga waahanga:

  1. Mahara Motuhake
  2. Kaiwhakahaere MotuhakeXilinx DDR2 MIG 7 Whakatau Mahinga-fig-20

Ko te Whakaaturanga 9 e tuku ana ki a koe he mutungaview o nga kupu e maumahara ana.
Kaore i rite ki nga SRAM me nga Maharatanga Poraka DDR2, DDR3 ranei, ehara i te mea ko te reeti raraunga teitei noa iho.

Ka whakawhirinaki ki te maha o nga waahi, tae atu ki:

  • tRCD: Row Command Row (ras to cas delay).
  • tCAS(CL): Rorohiko strobe wāhitau tīwae.
  • tRP: Roa i mua i te utunga haupae.
  • tRAS: Row Active Time (whakahohe ki te whakarereke).
  • tRC: Wā huringa haupae. tRC = tRAS + tRP
  • tRAC: Te roa o te urunga Radom. tRAC = tRCD + tCAS
  • tCWL: Tuhituhi cas tohenga.
  • tZQ: Te wa whakatikatika ZQ.
  • tRFC: Wā Porohita Tāmata Haupae
  • tWTR: Tuhia ki te Panui te roa. Tuhia te tauwhitinga whakamutunga ki te Panui te wa whakahau.
  • tWR: Tuhia te wa Whakaora. Tuhia te tauwhitinga whakamutunga ki te wa Utu-mua

Ko te taima o nga tawhā kua whakarārangihia e whakawhirinaki ana ki te momo pūmahara i whakamahia me te kōeke tere o te wahanga mahara.
Ka kitea etahi atu korero mo nga whakamaramatanga me nga whakaritenga wa i roto i te DDR2 DDR3 JEDEC, i roto ranei i tetahi papaaarangi taputapu mahara.

Ko te kaha ka whakawhirinaki ki te urunga o te mahara. Ko nga tauira wahitau rereke he rereke nga hua whai hua.

Nga wa mahara ki runga

  1. Te wa whakahohe me te wa Tomua i te wa e huri ana ki nga peeke/rarangi hou, ki te huri rarangi ranei i roto i te peeke kotahi.- Na ki te whakaiti koe i te huringa rarangi, ka taea e tenei te tango tRCD me te tRP.
  2. Tukuna tonu te tuhi, panui ranei nga whakahau -Maitaining tCCD timing.
  3. Whakaitihia te tuhi ki te panui me te panui ki te tuhi i nga huringa whakahau - Tuhia te wa whakaora ki te huri ki nga urunga panui, te wa huri pahi ki te huri mai i te panui ki te tuhi
  4. Whakaritea he waahi whakahou tika.
    • Ko te DDR3 SDRAM e hiahia ana ki nga huringa Refresh i te wa toharite o te tREFI.
    • Ka taea te tuku i mua ake i te 8 o nga whakahau Whakahou ("Kua mai"). Kaore tenei e whakaiti i te maha o nga whakamaarama, engari ko te waahi morahi i waenga i nga whakahau e rua a tawhio noa, he iti ki te 9 × tREFIXilinx DDR2 MIG 7 Whakatau Mahinga-fig-21
  • Whakamahia nga peeke katoa - He pai ake te tikanga whakatika.
    • Rarangi-Peeke-Tīwae: Mo te tauwhitinga ka puta i runga i te mokowā wāhitau raupapa, ka whakatuwhera aunoa te matua i te rarangi kotahi i te peeke o muri o te taputapu DRAM kia haere tonu te tauwhitinga ina tae ki te mutunga o te rarangi o mua. He tino pai ki nga tono e hiahia ana kia pakaru nga paanui raraunga nui ki nga waahi wahitau raupapa.
    • Peke-Rau-Tīwae: Ina whakawhiti i te rohe rarangi, ka kati te rarangi o naianei, ka whakatuwherahia tetahi atu rarangi i roto i te peeke kotahi. Ko te MSB he wahitau putea, ka taea te whakamahi ki te huri mai i nga peeke rereke. He pai mo nga whakawhitinga poto ake, matapōkeretia ki tetahi poraka mahara mo tetahi wa, ka peke ki tetahi atu poraka (peeke)
  • Roa Pahū
    • Kei te tautokohia te BL 8 mo te DDR3 i runga i te raupapa 7. He iti rawa te kaha o te BC4 he iti iho i te 50%. Na te mea he rite te wa mahi o BC4 ki te BL8. Ko nga raraunga ka huna noa i roto i te waahanga.
    • I nga keehi karekau koe e hiahia ki te tuhi i te pakarutanga katoa, ka taea te whakaaro ma te kopae raraunga me te tuhi-i muri i te panui.
  • Tautuhia he waahi ZQ tika (DDR3 Anake)
    Ka tukuna e te kaiwhakahaere nga whakahau Whakariterite ZQ Poto (ZQCS) me te ZQ Roa (ZQCL).
    • Kia mau ki te Paerewa DDR3 Jedec
    • Ko te ZQ Calibration e korerohia ana i te waahanga 5.5 o te JEDEC Spec JESD79-3 DDR3 SDRAM Paerewa
    • Ko te ZQ Calibration e whakataurite ana i te Whakamutunga Mate (ODT) i nga wa rite ki te whakaaro mo nga rereketanga puta noa i te VT
    • Ko te arorau kei roto bank_common.v/vhd
    • Ka whakatauhia e te Tawhā Tzqcs te reeti ka tukuna he tono Whakatau ZQ ki te mahara
    • Ka taea te whakakore i te porotiti me te tuku a-ringa ma te whakamahi i te app_zq_req, he rite ki te tuku a-ringa i te Refresh.
      Tirohia (Xilinx Whakautu 47924) mo nga taipitopito.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-22

Nga Kaipupuri Kaiwhakahaere

  1. Panui Waahanga – Tirohia (Whakautu Xilinx 43344) mo nga taipitopito.
    • Kaua e whakarereketia te wa o te panui
    • Hukahia nga panui i nga wa e tuhi ana ka tukuna te maha o nga panui kua ngaro i mua i te panui pono
  2. Te Whakaraupapa - Tirohia (Whakautu Xilinx 34392) mo nga taipitopito.
    Mo nga hoahoa Atanga Kaiwhakamahi me te Atanga AXI he pai ake kia whakahohea tenei.
    • Ko te raupapa ano te arorau e titiro whakamua ana ki te maha o nga whakahau me te whakarereke i te raupapa whakahau a te kaiwhakamahi kia kore ai nga whakahau mahara-kore e noho i te bandwidth whaimana. Ko te mahinga e pa ana ki te tauira waka.
    • I runga i te tauira wahitau, ka awhina ano te raupapa ki te peke i te utu o mua me te whakahohe i nga whakahau me te kore e noho te tRCD me te tRP i te whanui roopu raraunga.Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-23
  3. Ngana ki te whakanui ake i te maha o nga Miihini Peeke.
    • Ko te nuinga o te arorau a te kaiwhakahaere kei roto i nga miihini peeke ka rite ki nga peeke DRAM
    • Ka whakahaerehia e te miihini peeke tetahi peeke DRAM kotahi i nga wa katoa.
    • He hihiri te mahi miihini peeke no reira kaore e tika kia whai miihini peeke mo ia peeke tinana.
    • Ka taea te whirihora i nga miihini peeke, engari he tauhokohoko i waenga i te waahi me te mahi.
    • Ko te maha o nga miihini putea e whakaaetia ana mai i te 2-8.
    • Ma te taunoa, ka whirihorahia nga Miihini Peeke 4 ma nga taapiri RTL.
    • Hei huri i nga Miihini Peeke, whakaarohia te tawhā nBANK_MACHS = 8 kei roto i te memc_ui_top Exampmo nga Miihini Peeke 8 - nBANK_MACHS = 8

Kei te mohio koe inaianei ki nga ahuatanga e awe ana i nga mahi.
Whakaarohia he tono whakarunga e hoatu ana ki a koe te 512 paita raraunga mo ia paatete, me tiaki e koe ki nga waahi mahara rereke. I te 512 raraunga paita he rite ki te 64 DDR3 pakaru raraunga, whakahaere ano te exampte hoahoa me te whakaongaonga file kei roto 512 tuhi, 512 panui me te huri haupae mo ia 64 tuhi, panui ranei:

  • 3f_0_0_0000_000_0
  • 3f_0_0_0001_000_0
  • 3f_0_0_0002_000_0
  • 3f_0_0_0003_000_0
  • 3f_0_0_0004_000_0
  • 3f_0_0_0005_000_0
  • 3f_0_0_0006_000_0
  • 3f_0_0_0007_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_0_0001_000_1
  • 3f_0_0_0002_000_1
  • 3f_0_0_0003_000_1
  • 3f_0_0_0004_000_1
  • 3f_0_0_0005_000_1
  • 3f_0_0_0006_000_1
  • 3f_0_0_0007_000_1

I te mutunga o te whaihanga ka kite koe kei te 77 paiheneti te whakamahi pahi. Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-24

Whakaahua 11: Nga Tauanga Mahinga mo te 512 tuhi me te 512 panui - Te huri rarangi mo te 64 tuhi, panui ranei. 

Ka taea e koe te whakamahi i nga matauranga i akohia i te waahanga o mua hei whakapai ake i te pai. Me a view ki te whakamahi i nga peeke katoa hei utu mo te whakarereke i te rarangi, whakarereke i te tauira wahitau hei huri i te peeke penei i raro nei.
He rite tenei ki te whakatakoto i te ROW_BANK_Column i roto i te tautuhinga mapi wahitau mahara ki te MIG GUI.

  • 3f_0_0_0000_000_0
  • 3f_0_1_0000_000_0
  • 3f_0_2_0000_000_0
  • 3f_0_3_0000_000_0
  • 3f_0_4_0000_000_0
  • 3f_0_5_0000_000_0
  • 3f_0_6_0000_000_0
  • 3f_0_7_0000_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_1_0000_000_1
  • 3f_0_2_0000_000_1
  • 3f_0_3_0000_000_1
  • 3f_0_4_0000_000_1
  • 3f_0_5_0000_000_1
  • 3f_0_6_0000_000_1
  • 3f_0_7_0000_000_1

I te mutunga o te whaihanga ka kite koe ko te 77 Percent Bus Utilization o mua ko 87 inaianei! Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-25

Mena kei te hiahia koe kia kaha ake te mahi, ka taea e koe te haere mo nga rahinga paanui 1024, 2048 paita ranei, ka whakaaro ranei ki te whakahou a-ringa.

Tuhipoka: Kare a Xilinx e akiaki i te aukati i te whakahou i te kaiwhakahaere na te mea kaore matou i te mohio mena ka taea e koe te whakatau i te waa whakahou aunoa a Jedec e pa ana ki te pono o nga raraunga.
Mai i te taha o te kaiwhakahaere ka taea e koe te huri i te nBANk_MACH ka kite i te whakapai ake i te mahi.
Heoi, ka pa pea tenei ki to wa hoahoa, tirohia koa (Whakautu Xilinx 36505) mo nga korero mo nBANk_MACHXilinx DDR2 MIG 7 Whakatau Mahinga-fig-26

Whakatuwheratia te ingoa_kaupapa_mig_sim.v file ka huri i nga tawhā nBANK_MACHS mai i te 4 ki te 8 me te whakahaere ano i te whaihanga. Kia whai mana ai te uara tawhā i roto i te taputapu, me whakahōu koe i te core_name_mig.v file.
I whakamahia e au te tauira ano i whiwhi matou i te 87% te whakamahi pahi (ahua -12).
Ma te nBANK_MACHS kua whakaritea ki te 8, ko te kaha inaianei ko 90%. Xilinx DDR2 MIG 7 Whakatau Mahinga-fig-27

Me tuhi ano ko te ½ me te ¼ nga kaiwhakahaere ka pa kino ki te pai na runga i o raatau waahi.
Mo te exampNa, i te mea ka taea noa e matou te tuku whakahau ia 4 huringa CK i etahi wa he taapiri taapiri ina piri ana ki nga tohu taima DRAM iti, ka taea te whakaiti i te kaha mai i te kaupapa.
Whakamātauria ngā pūmana rerekē ki te kimi i te mea e pai ana ki to hiahia.

Tohutoro

  1. Zynq-7000 AP SoC me nga Rangatū 7 FPGA MIS v2.3 [UG586]
  2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Tuhinga o mua
13/03/2015 – Tukunga tuatahi

Tangohia te PDF: Xilinx DDR2 MIG 7 Aratohu Whakatau Mahinga

Tohutoro

Whakairinga Paanga

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