25G Ethernet Intel® FPGA IP Release Notes
Aratohu Kaiwhakamahi
25G Ethernet Intel FPGA IP Release Notes (Nga Pūrere Intel Agilex)
Ko nga putanga Intel® FPGA IP e rite ana ki nga putanga rorohiko Intel Quartus® Prime Design Suite tae noa ki te v19.1. Ka timata i roto i te putanga rorohiko Intel Quartus Prime Design Suite 19.2, he kaupapa whakaputa hou a Intel FPGA IP.
Ka huri te tau Intel FPGA IP (XYZ) me ia putanga rorohiko Intel Quartus Prime. He huringa i roto i:
- Ko te X e tohu ana i te whakahounga nui o te IP. Mena ka whakahouhia e koe te rorohiko Intel Quartus Prime, me whakahou e koe te IP.
- E tohu ana te IP kei roto nga ahuatanga hou. Whakahouhia to IP ki te whakauru i enei ahuatanga hou.
- Ka tohu a Z kei roto i te IP nga huringa iti. Whakahoutia to IP ki te whakauru i enei huringa.
1.1. 25G Itarangi Intel FPGA IP v1.0.0
Ripanga 1. v1.0.0 2022.09.26
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 22.3 | He tautoko taapiri mo te whanau taputapu Intel Agilex™ F-tile. • Ko te tere tere 25G anake e tautokohia ana. • Ko te 1588 Precision Time Protocol e kore e tautokona. |
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Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. *Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.
ISO
9001:2015
Kua rehitatia
25G Ethernet Intel FPGA IP Release Notes (Intel Stratix 10 Pūrere)
Mena kaore he tuhipoka tuku i te waatea mo tetahi putanga IP motuhake, kaore he huringa o te IP i taua putanga. Mo nga korero mo nga putanga whakahou IP ki runga ki te v18.1, tirohia te Intel Quartus Prime Design Suite Update Release Notes.
Ko nga putanga Intel FPGA IP e rite ana ki nga putanga rorohiko Intel Quartus Prime Design Suite tae noa ki te v19.1. Ka timata i roto i te putanga rorohiko Intel Quartus Prime Design Suite 19.2, Intel
He kaupapa whakaputa hou a FPGA IP.
Ka huri te tau Intel FPGA IP (XYZ) me ia putanga rorohiko Intel Quartus Prime. He huringa i roto i:
- Ko te X e tohu ana i te whakahounga nui o te IP. Mena ka whakahouhia e koe te rorohiko Intel Quartus Prime, me whakahou e koe te IP.
- E tohu ana te IP kei roto nga ahuatanga hou. Whakahouhia to IP ki te whakauru i enei ahuatanga hou.
- Ka tohu a Z kei roto i te IP nga huringa iti. Whakahoutia to IP ki te whakauru i enei huringa.
Nga korero e pa ana
- Intel Quartus Prime Design Suite Update Release Notes
- 25G Itarangi Intel Stratix®10 FPGA IP Aratohu Kaiwhakamahi Archives
- 25G Itarangi Intel Stratix® 10 FPGA IP Hoahoa Example Archives Aratohu Kaiwhakamahi
- Errata mo te 25G Ethernet Intel FPGA IP i roto i te Papa Matauranga
2.1. 25G Itarangi Intel FPGA IP v19.4.1
Ripanga 2. v19.4.1 2020.12.14
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 20.4 | Te roanga arowhai whakahōutanga ki ngā tāpare VLAN: • I nga putanga o mua o 25G Ethernet Intel FPGA IP, ka whakapaehia te hapa anga nui ina tutuki nga tikanga e whai ake nei: 1. VLAN a. Kua whakahohea te kitenga VLAN. b. Ka tuku/kawe te IP i nga papa me te roa ki te morahi te roa o te anga TX/RX me te 1 ki te 4 octets. 2. SVLAN a. Kua whakahohea te rapunga SVLAN. b. Ka tuku/kawe te IP i nga papa me te roa ki te morahi te roa o te anga TX/RX me te 1 ki te 8 octets. • I tenei putanga, ka whakahouhia te IP hei whakatika i tenei whanonga. |
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| I whakahōuhia te urunga atanga mapi-mahara-a Avalon® ki te atanga status_* hei aukati i te waahi kua mapi-maharatia a Avalon i te wa e panui ana ki nga waahi noho kore: • I roto i nga putanga o mua o 25G Ethernet Intel FPGA IP, ka panui te atanga mapi-mahara a Avalon ki nga wahitau kore-kore i runga i te atanga status_* ka kii i te status_waitrequest kia pau ra ano te tono a te rangatira o Avalon memorymapped. Inaianei kua whakatikahia te take kia kaua e mau ki te tatari kia uru atu he wahi noho kore. |
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| Ko nga momo rereke kua whakahohea e RS-FEC e tautoko ana i te 100% te whakaputa. | — |
2.2. 25G Itarangi Intel FPGA IP v19.4.0
Ripanga 3. v19.4.0 2019.12.16
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 19.4 | huringa whanonga rx_am_lock: • I nga putanga o mua o te 25G Ethernet Intel FPGA IP, he rite te ahua o te tohu rx_am_lock ki te rx_block_lock puta noa i nga momo rereke katoa. • I roto i tenei putanga, mo nga momo IP kua whakahohea e te RSFEC, ka kii a rx_am_lock ka tutuki te raka tirohanga. Mo nga momo rereke kore-RSFEC, he rite tonu te ahua o te rx_am_lock ki te rx_block_lock. |
Ko te tohu atanga, rx_am_lock, he rereke te ahua mai i nga putanga o mua mo nga momo rereke e taea ana e te RSFEC. |
| Kua whakahōuhia te RX MAC Tīmatatanga o te Pākete: • I nga putanga o mua, ko te RX MAC anake te tirotiro mo te ahua TITIAKI hei whakatau i te timatanga o te kete. • I roto i tenei putanga, ka tirohia e te RX MAC inaianei mo nga paatete taumai mo te Start of Frame Delimiter (SFD), i tua atu i te tohu TIMA ma te taunoa. • Mēnā ka whakahohea te aratau whakawhiti kupu whakataki, ka tirohia e te MAC anake te pūāhua TIMA kia taea ai te whakataki ritenga. |
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| Kua taapirihia he rehita hou kia taea ai te arowhai korero: • I roto i nga rehita RX MAC, ka taea te tuhi i te rehita i offset 0x50A [4] ki te 1 kia taea ai te arowhai korero. Ko tenei rehita he "kaore e aro" ina whakahohea te kupu whakataki. |
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2.3. 25G Itarangi Intel FPGA IP v19.3.0
Ripanga 4. v19.3.0 2019.09.30
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 19.3 | Mo te momo MAC+PCS+PMA, kua hanga hihiri te ingoa kōwae takai whakawhiti. Ma tenei ka aukati i te tukinga kōwae e kore e hiahiatia mena kei te whakamahia nga tauira maha o te IP i roto i te punaha. | — |
2.4. 25G Itarangi Intel FPGA IP v19.2.0
Ripanga 5. v19.2.0 2019.07.01
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 19.2 | Hoahoa Exampmo te 25G Ethernet Intel FPGA IP: • I whakahōuhia te kōwhiringa kete whanaketanga whainga mo nga taputapu Intel Stratix® 10 mai i Intel Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit ki Intel Stratix 10 10 GX Signal Integrity L-Tile (Whakaputa) Kete Whakawhanaketanga. |
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2.5. 25G Itarangi Intel FPGA IP v19.1
Ripanga 6. v19.1 Paenga-whāwhā 2019
| Whakaahuatanga | Pānga |
| Kua taapirihia he waahanga hou - aratau urutau mo te RX PMA Adaptation: • Kua taapirihia he tawhā hou—Whakahohe te urutau aunoa mo te aratau RX PMA CTLE/DFE. |
Ko enei huringa he mea whiriwhiri. Ki te kore koe e whakapai ake i to matua IP, karekau tenei waahanga hou. |
| I whakaingoatia ano te tawhā Whakahohe Altera Debug Master Endpoint (ADME) ki te Whakahohe Native PHY Debug Master Endpoint (NPDME) kia rite ki te tohu hou a Intel i roto i te rorohiko Intel Quartus Prime Pro Edition. Kei te whakamahi tonu te rorohiko Intel Quartus Prime Standard Edition Whakahohe Altera Debug Master Endpoint (ADME). | — |
2.6. 25G Itarangi Intel FPGA IP v18.1
Ripanga 7. Putanga 18.1 Mahuru 2018
| Whakaahuatanga | Pānga |
| Kua taapirihia he waahanga hou—PMA whiriwhiri: • Tāpirihia he tawhā hōu—He rerekētanga matua. |
Ko enei huringa he mea whiriwhiri. Ki te kore koe e whakapai ake i to matua IP, karekau enei ahuatanga hou. |
| • I taapirihia he tohu hou mo 1588 Atanga Kawa Tika Tika—latency_sclk. | |
| Hoahoa Exampmo te 25G Ethernet Intel FPGA IP: I whakaingoatia te whiringa kete whanaketanga whaainga mo nga taputapu Intel Stratix 10 mai i Stratix 10 GX FPGA Development Kit ki Stratix 10 L-Tile GX Transceiver Signal Development Kit. |
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Nga korero e pa ana
- 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi
- 25G Itarangi Intel Stratix 10 FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi
- Errata mo te 25G Ethernet IP matua i roto i te Papa Matauranga
2.7. 25G Itarangi Intel FPGA IP v18.0
Ripanga 8. Putanga 18.0 Haratua 2018
| Whakaahuatanga | Pānga |
| Tukunga tuatahi mo nga taputapu Intel Stratix 10. | — |
2.8. 25G Itarangi Intel Stratix 10 FPGA IP Kaiwhakamahi Aratohu Archives
He rite nga putanga IP ki nga putanga rorohiko Intel Quartus Prime Design Suite ki te v19.1. Mai i te putanga rorohiko Intel Quartus Prime Design Suite 19.2 i muri mai ranei, he kaupapa whakaputa IP hou nga konae IP.
Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.
| Intel Quartus Prime Putanga | Putanga Matua IP | Aratohu Kaiwhakamahi |
| 20.3 | 19.4.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 20.1 | 19.4.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 19.4 | 19.4.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 19.3 | 19.3.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 19.2 | 19.2.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 19.1 | 19.1 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 18.1 | 18.1 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
| 18.0 | 18.0 | 25G Itarangi Intel Stratix 10 FPGA IP Aratohu Kaiwhakamahi |
2.9. 25G Itarangi Intel Stratix 10 FPGA IP Hoahoa Example Archives Aratohu Kaiwhakamahi
He rite nga putanga IP ki nga putanga rorohiko Intel Quartus Prime Design Suite ki te v19.1. Mai i te putanga rorohiko Intel Quartus Prime Design Suite 19.2 i muri mai ranei, he kaupapa whakaputa IP hou nga konae IP.
Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.
| Intel Quartus Prime Putanga | Putanga Matua IP | Aratohu Kaiwhakamahi |
| 19.1 | 19.1 | 25G Itarangi Intel Stratix 10 FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi |
| 18.1 | 18.1 | 25G Itarangi Intel Stratix 10 FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi |
| 18.0 | 18.0 | 25G Itarangi Intel Stratix 10 FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi |
25G Ethernet Intel FPGA IP Release Notes (Intel Arria 10 Pūrere)
Mena kaore he tuhipoka tuku i te waatea mo tetahi putanga IP motuhake, kaore he huringa o te IP i taua putanga. Mo nga korero mo nga putanga whakahou IP ki runga ki te v18.1, tirohia te Intel Quartus Prime Design Suite Update Release Notes.
Ko nga putanga Intel FPGA IP e rite ana ki nga putanga rorohiko Intel Quartus Prime Design Suite tae noa ki te v19.1. Ka timata i roto i te putanga rorohiko Intel Quartus Prime Design Suite 19.2, he kaupapa whakaputa hou a Intel FPGA IP.
Ka huri te tau Intel FPGA IP (XYZ) me ia putanga rorohiko Intel Quartus Prime. He huringa i roto i:
- Ko te X e tohu ana i te whakahounga nui o te IP. Mena ka whakahouhia e koe te rorohiko Intel Quartus Prime, me whakahou e koe te IP.
- E tohu ana te IP kei roto nga ahuatanga hou. Whakahouhia to IP ki te whakauru i enei ahuatanga hou.
- Ka tohu a Z kei roto i te IP nga huringa iti. Whakahoutia to IP ki te whakauru i enei huringa.
Nga korero e pa ana
- Intel Quartus Prime Design Suite Update Release Notes
- 25G Itarangi Intel Arria® 10 FPGA IP Aratohu Kaiwhakamahi
- 25G Itarangi Intel Arria® 10 FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi
- Errata mo te 25G Ethernet Intel FPGA IP i roto i te Papa Matauranga
3.1. 25G Itarangi Intel FPGA IP v19.4.1
Ripanga 9. v19.4.1 2020.12.14
| Intel Quartus Putanga Pirimia | Whakaahuatanga | Pānga |
| 20.4 | Te roanga arowhai whakahōutanga ki ngā tāpare VLAN: • I nga putanga o mua o 25G Ethernet Intel FPGA IP, ka whakapaehia te hapa anga nui ina tutuki nga tikanga e whai ake nei: 1. VLAN a. Kua whakahohea te kitenga VLAN. b. Ka tuku/kawe te IP i nga papa me te roa ki te morahi te roa o te anga TX/RX me te 1 ki te 4 octets. 2. SVLAN a. Kua whakahohea te rapunga SVLAN. b. Ka tuku/kawe te IP i nga papa me te roa ki te morahi te roa o te anga TX/RX me te 1 ki te 8 octets. • I tenei putanga, ka whakahouhia te IP hei whakatika i tenei whanonga. |
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| I whakahōuhia te urunga atanga mapi-mahara-a-Avalon ki te atanga status_* hei aukati i te waahi-mahere a Avalon i te wa e panui ana ki nga waahi noho kore: • Ka whakahōuhia te IP ki te whakakore i te tono tatari ina uru mai he wahitau kore-kore ki te atanga status_*. |
3.2. 25G Itarangi Intel FPGA IP v19.4.0
Ripanga 10. v19.4.0 2019.12.16
| Intel Quartus Prime Putanga | Whakaahuatanga | Pānga |
| 19.4 | huringa whanonga rx_am_lock: • I nga putanga o mua o te 25G Ethernet Intel FPGA IP, he rite te ahua o te tohu rx_am_lock ki te rx_block_lock puta noa i nga momo rereke katoa. • I roto i tenei putanga, mo nga momo IP kua whakahohea e te RSFEC, ka kii a rx_am_lock ka tutuki te raka tirohanga. Mo nga momo rereke kore-RSFEC, he rite tonu te ahua o te rx_am_lock ki te rx_block_lock. |
Ko te tohu atanga, rx_am_lock, he rereke te ahua mai i nga putanga o mua mo nga momo rereke e taea ana e te RSFEC. |
| Kua whakahōuhia te RX MAC Tīmatatanga o te Pākete: • I nga putanga o mua, ko te RX MAC anake te tirotiro mo te ahua TITIAKI hei whakatau i te timatanga o te kete. • I roto i tenei putanga, ka tirohia e te RX MAC inaianei mo nga paatete taumai mo te Start of Frame Delimiter (SFD), i tua atu i te tohu TIMA ma te taunoa. • Mēnā ka whakahohea te aratau whakawhiti kupu whakataki, ka tirohia e te MAC anake te pūāhua TIMA kia taea ai te whakataki ritenga. |
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| Kua taapirihia he rehita hou kia taea ai te arowhai korero: • I roto i nga rehita RX MAC, ka taea te tuhi i te rehita i offset 0x50A [4] ki te 1 kia taea ai te arowhai korero. Ko tenei rehita he "kaore e aro" ina whakahohea te kupu whakataki. |
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3.3. 25G Itarangi Intel FPGA IP v19.1
Ripanga 11. v19.1 Paenga-whāwhā 2019
| Whakaahuatanga | Pānga |
| I whakaingoatia ano te tawhā Whakahohe Altera Debug Master Endpoint (ADME) ki te Whakahohe Native PHY Debug Master Endpoint (NPDME) kia rite ki te tohu hou a Intel i roto i te rorohiko Intel Quartus Prime Pro Edition. Kei te whakamahi tonu te rorohiko Intel Quartus Prime Standard Edition Whakahohe Altera Debug Master Endpoint (ADME). | — |
3.4. 25G Itarangi IP Core v17.0
Ripanga 12. Putanga 17.0 Haratua 2017
| Whakaahuatanga | Pānga |
| He taapiri atarangi mo te panui i nga rehita tatauranga. • I roto i nga rehita tatauranga TX, whakakapihia te rehita CLEAR_TX_STATS i te 0x845 ki te rehita CNTR_TX_CONFIG hou. Ka taapirihia e te rehita hou he tono whakamarumaru me te moka maramara-hapa-parerite ki te moka e whakawātea ana i nga rehita tatauranga TX katoa. Kua taapirihia he rehita CNTR_RX_STATUS hou ki te 0x846, kei roto he moka hapa-whakarite me te moka mana mo te tono atarangi. • I roto i nga rehita tatauranga RX, whakakapihia te rehita CLEAR_RX_STATS i te 0x945 ki te rehita CNTR_RX_CONFIG hou. Ka taapirihia e te rehita hou he tono whakamarumaru me tetahi moka maramara hapa-parite ki te moka. ka whakakore i nga rehita tatauranga TX katoa. Kua taapirihia he rehita CNTR_TX_STATUS hou ki te 0x946, kei roto he moka parite-hapa me te moka mana mo te tono atarangi. |
Ko te ahuatanga hou e tautoko ana i te pai ake o te pono i roto i nga panui kaute tatauranga. Hei panui i te porotiti tatauranga, tuatahi tautuhia te moka tono atarangi mo tera huinga rehita (RX, TX ranei), ka panui mai i te whakaahua o te rehita. Ka mutu te piki haere o nga uara panui i te wa e mau ana te ahua o te atarangi, engari ka piki haere tonu nga porotiti o raro. Whai muri i to tautuhi i te tono, ka hoki ano nga porotiti i o raatau uara kua whakaemihia. I tua atu, kei roto i nga mara rehita hou te mana hapa hapa me nga moka marama. |
| I whakarereketia te whakatakotoranga tohu tirohanga RS-FEC kia u ki te rara 108 kua oti te whakaoti inaianei o te IEEE 802.3by whakaritenga. I mua ko te waahanga RS-FEC i tutuki ki te 25G/50G Consortium Schedule 3, i mua i te IEEE te whakaotinga whakaritenga. |
Inaianei ka kitea e te RX RS-FEC me te raka ki nga tohu whakatiaroaro tawhito me te hou, engari ko te TX RS-FEC anake te hanga i te whakatakotoranga tohu tirohanga IEEE hou. |
Nga korero e pa ana
- 25G Itarangi IP Aratohu Kaiwhakamahi Matua
- Errata mo te 25G Ethernet IP matua i roto i te Papa Matauranga
3.5. 25G Itarangi IP Core v16.1
Ripanga 13. Putanga 16.1 Oketopa 2016
| Whakaahuatanga | Pānga |
| Tukunga tuatahi i roto i te Intel FPGA IP Library. | — |
Nga korero e pa ana
- 25G Itarangi IP Aratohu Kaiwhakamahi Matua
- Errata mo te 25G Ethernet IP matua i roto i te Papa Matauranga
3.6. 25G Itarangi Intel Arria® 10 FPGA IP Kaiwhakamahi Aratohu Pūranga
He rite nga putanga IP ki nga putanga rorohiko Intel Quartus Prime Design Suite ki te v19.1. Mai i te putanga rorohiko Intel Quartus Prime Design Suite 19.2 i muri mai ranei, he kaupapa whakaputa IP hou nga konae IP.
Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.
| Intel Quartus Prime Putanga | Putanga IP | Aratohu Kaiwhakamahi |
| 20.3 | 19.4.0 | 25G Itarangi Intel Arria® 10 FPGA IP Aratohu Kaiwhakamahi |
| 19.4 | 19.4.0 | 25G Itarangi Intel Arria 10 FPGA IP Aratohu Kaiwhakamahi |
| 17.0 | 17.0 | 25G Itarangi Intel Arria 10 FPGA IP Aratohu Kaiwhakamahi |
3.7. 25G Itarangi Intel Arria 10 FPGA IP Hoahoa Exampte Kaiwhakamahi Aratohu Archives
He rite nga putanga IP ki nga putanga rorohiko Intel Quartus Prime Design Suite ki te v19.1. Mai i te putanga rorohiko Intel Quartus Prime Design Suite 19.2 i muri mai ranei, he kaupapa whakaputa IP hou nga konae IP.
Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.
| Intel Quartus Prime Putanga | Putanga Matua IP | Aratohu Kaiwhakamahi |
| 16.1 | 16.1 | 25G Itarangi Hoahoa Exampte Aratohu Kaiwhakamahi |
25G Ethernet Intel® FPGA IP Release Notes
Putanga Ingarihi
Tuku Urupare
ID: 683067
Putanga: 2022.09.26
Tuhinga / Rauemi
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intel 25G Itarangi Intel FPGA IP [pdf] Aratohu Kaiwhakamahi 25G Itarangi Intel FPGA IP, Itarangi Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |