Te Waihanga i nga Pūnaha Mahara Heterogene ki te FPGA SDK mo nga Papahanga Ritenga OpenCL
Tohutohu

Te Waihanga Pūnaha Mahara Heterogene i roto i te Intel® FPGA SDK mo nga Papahanga Ritenga OpenCL

Ko te whakatinanatanga o te mahara rereke i roto i te Ritenga Ritenga ka taea te nui ake o te atanga mahara o waho (EMIF) tae atu ki nga urunga mahara nui ake me te tere ake. Ko te huinga o te uru mahara heterogenous ki te papaitia
Ka taea e OpenCL ™(1)kernel te whakapai ake i nga mahi mo to punaha OpenCL.
Ko tenei tuhipoka tono he arahi mo te hanga i nga punaha mahara rereke i roto i te Papa Ritenga hei whakamahi me te Intel® FPGA SDK mo OpenCL(2). Kei te whakaaro a Intel he kaihoahoa mohio koe mo te FPGA e whakawhanake ana i nga Paerewa Ritenga kei roto nga punaha mahara rereke.
I mua i te hanga i nga punaha mahara rereke, kia mohio koe ki te Intel FPGA SDK mo nga tuhinga OpenCL kua tohua i raro nei.
Nga korero e pa ana

• Intel FPGA SDK mo OpenCL Papatono Aratohu
• Intel FPGA SDK mo OpenCL Aratohu Mahi Pai
• Intel FPGA SDK mo OpenCL Arria 10 GX FPGA Whanaketanga Kete Tohutoro Aratohu Tauranga Paerewa

1.1. Te Manatoko i te Mahi o te Poari FPGA me nga Atanga EMIF

Manatokohia ia atanga mahara katahi ka whakamohio i to Paerewa Ritenga ma te whakamahi i te mahara o te ao.

1. Manatokohia ia atanga mahara ma te whakamahi i nga hoahoa taputapu hei whakamatautau i te tere me te pumau o ia atanga.
2. Whakakotahitia to Paerewa Ritenga ma te whakamahi i te mahara o te ao.
   1. Mo te exampNa, ki te toru nga atanga DDR koe, me mapi tetahi o enei hei maharatanga rerekee. I tenei keehi, manatokohia te mahi o te puranga OpenCL me ia atanga DDR takitahi.
      Ko OpenCL me te moko OpenCL he tohu hokohoko na Apple Inc. i whakamahia ma te whakaaetanga a te Khronos Group™ .
   2.  Ko te Intel FPGA SDK mo OpenCL e ahu mai ana i runga i te Khronos Specification kua whakaputaina, a kua paahitia te Khronos Conformance Testing Process. Ka kitea te ahuatanga o naianei i www.khronos.org/conformance.

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. *Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.
ISO 9001:2015 Kua Rehitatia
Hei tauira, mena e rua nga atanga DDR me tetahi atanga reiti raraunga tapawha (QDR), manatokohia te mahi o te puranga OpenCL o nga atanga DDR e rua me te atanga QDR takitahi.
E taunaki ana a Intel me whakamahi koe i te PCI Express® – (PCIe® -) ranei i nga hoahoa EMIF-motuhake hei whakamatautau i o atanga mahara. Whai muri i to manatoko kei te mahi ia atanga mahara me te mahi o to hoahoa OpenCL me tetahi waahanga o nga atanga mahara, haere tonu
ki te hanga i tetahi punaha mahara heterogeneous tino mahi. 
1.2. Te whakarereke i te board_spec.xml File
Whakakēhia te board_spec.xml file ki te tautuhi i nga momo punaha mahara rereke e waatea ana ki nga kakano OpenCL.
I te wa o te whakahiato pata, ka tautapahia e te Intel FPGA SDK mo OpenCL Offline Compiler nga tohenga kernel ki tetahi mahara i runga i te tohenga tauwāhi papaa e tohua ana e koe.
1. Tirotiro ki te board_spec.xml file i roto i te whaiaronga taputapu o to Paerewa Ritenga.
2. Whakatuwheratia te board_spec.xml file i roto i te ētita kuputuhi me te whakarereke i te XML kia rite.
Mo te exampNa, ki te mea e rua nga maharatanga DDR o to punaha taputapu hei maharatanga ao taunoa me nga peeke QDR e rua ka whakatauirahia e koe hei mahara rereke, whakarereke i nga waahanga mahara o te board_spec.xml file kia rite ki enei e whai ake nei:
















1.3. Te Whakaritea Nga Kaiwehe Mahara Maha i Qsys
I tenei wa, ko te OpenCL Memory Bank Divider i roto i te hoahoa Qsys kaore i te tautoko i te mana-o-2 te maha o nga peeke mahara, ehara i te mea he herenga mo nga whirihoranga angamaheni. Heoi ano, tera ano nga ahuatanga e tika ana kia kore te mana-o-2 o nga atanga mahara. Hei whakauru i te maha o nga atanga mahara-kore-a-2, whakamahia nga Kaiwehewehe Peke Mahara OpenCL maha ki te hanga i nga punaha mahara rereke me te kore-mana-o-2 tau o nga peeke mahara. Me hanga e koe nga Wehewehenga Peke Mahara OpenCL maha ina he punaha mahara rereke pono koe. Whakaarohia he punaha me tetahi atanga mahara DDR me tetahi atanga mahara QDR. Na te mea he rereke nga topologies mahara o nga peeke e rua, kaore e taea e koe te whakakotahi i raro i te mahara kotahi o te ao.
Whakaatu 1. Hoahoa Poraka o te Pūnaha Mahara Heterogene E toru-Peeke
Kei roto i tenei punaha mahara rereke e rua nga atanga mahara DDR me tetahi atanga mahara QDR.Mena kei te whakamahi koe i te putanga 16.0, 16.0.1, 16.0.2 ranei o te rorohiko Intel Quartus® Prime me te Altera SDK mo OpenCL, kei te he te whakahaere a te OpenCL Memory Bank Divider i nga pakaru mahara puta noa i nga rohe wahitau. Hei mahi mo tenei take e mohiotia ana, taapirihia he piriti paipa me te rahi pakaru o te 1 ka hono atu i tana rangatira Avalon ®Memory-Mapped (Avalon-MM) ki te tauranga pononga a OpenCL Memory Bank Divider.
Tuhipoka:
Ko tenei take e mohiotia ana kua whakatikahia i roto i te rorohiko Intel Quartus Prime me te Intel FPGA SDK mo OpenCL putanga 16.1.
Whakaatu 2. Hoahoa Poraka o te Pūnaha Mahara Heterogene E toru-Peeke me te Piriti Pipeline 1.4. Te Whakarereke i te Papatono Whakamātautau Poari me te Waehere Kaihautū mo To Otinga Mahara Heterogene
Whakamahia te kakano boardtest.cl ka tae mai me te Intel FPGA SDK mo OpenCL Custom Platform Toolkit hei whakamatautau i te mahi me te mahinga o to Papai Ritenga.
Ko te hotaka whakamatautau poari he kakano OpenCL e taea ai e koe te whakamatautau i te whanui-nui-ki-te-taputapu, te bandwidth mahara, me te mahi whanui o to Ritenga Ritenga.

1. Tirotiro ki te /board/ custom_platform_toolkit/tests/boardtest directory.
2. Whakatuwheratia te boardtest.cl file i roto i te ētita kuputuhi me te tautapa i te waahi papaa ki ia tohenga mahara o te ao.
   Mo te example:
   __kernel kore
   mem_stream (__global__huanga__((buffer_location(“DDR”))) uint *src, __global __attribute__((buffer_location(“QDR”))) uint *dst, uint arg, uint arg2)
   I konei, ka tohua te uint *src ki te mahara DDR, ka tohua te uint *dst ki te mahara QDR. Ko te board_spec.xml file ka tohu i nga ahuatanga o nga punaha mahara e rua.
3. Hei whakamahi i to otinga mahara rereke i roto i to punaha OpenCL, whakarereke i to waehere kaihautu ma te taapiri i te haki CL_MEM_HETEROGENEOUS_INTELFPGA ki to waea clCreateBuffer.
   Mo te example:
   ddatain = clCreateBuffer(horopaki, CL_MEM_READ_WRITE | tohu tohu
   CL_MEM_HETEROGENEOUS_INTELFPGA, rahinga(kaore i hainatia) * Rahi vector, NULL, &tūnga);
   Kei te tino taunaki a Intel kia tautuhia e koe te waahi parepare hei tohenga kernel i mua i te tuhi i te parapara. I te wa e whakamahi ana koe i te maharatanga o te ao kotahi, ka taea e koe te tuhi i nga parepare i mua, i muri ranei i te tautapa ki te tohenga kernel. I roto i nga punaha mahara rereke, ka whakatauhia e te kaihautu te waahi papaa i mua i te tuhi i te papaa. I etahi atu kupu, ka karangahia e te kaihautu te mahi clSetKernelArgument i mua i te karanga i te mahi clEnqueueWriteBuffer.
   I roto i to waehere kaihautu, tonohia nga waea clCreateBuffer, clSetKernelArg, me clEnqueueWriteBuffer i roto i te raupapa e whai ake nei:
   ddatain = clCreateBuffer(horopaki, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, rahinga(kaore i hainatia) * Rahi vector, NULL, &tūnga);
   … tūnga = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (kore*)&ddatain);
   … tūnga = clEnqueueWriteBuffer(tutira, ddatain, CL_FALSE, 0, rahinga(kaore i haina) * vectorRahi, hdatain, 0, NULL, NULL);
   Ko te ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file he rite te raupapa o enei waea mahi.
4.  I muri i to whakarereke i te boardtest.cl file me te waehere kaihautu, whakahiatohia te kaihautu me te waehere kernel me te manatoko i o raatau mahi.
   I te wa e whakahiato ana i to waehere kernel, me whakakore e koe te pakaru-whakawhitinga o nga punaha mahara katoa ma te whakauru i te -kore-whakawhiti. kōwhiringa i roto i te whakahau aoc.

Nga korero e pa ana
Te Whakakore i te Burst-Interleaving o te Mahara o te Ao (–kaore he urunga )

1.5. Manatoko i te Taumahinga o To Mahara Heterogene Pūnaha
Hei whakarite kia pai te mahi a te punaha mahara rereke, wetewete i te haki CL_CONTEXT_COMPILER_MODE_INTELFPGA i to waehere kaihautu.
I roto i nga punaha OpenCL me te mahara riterite, me whiriwhiri koe ki te tautuhi i te haki CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 ki to waehere kaihautu kia whakakorehia te panui o te .aocx file me te reprogramming o te FPGA. Ko te whakatakoto i te haki CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 ka whai hua i te wa e toha ana to papa ki te manatoko i te mahi o to Papai Ritenga me te kore e hoahoa i te mahere papa me te tohu i nga rohe LogicLock™.
Me nga punaha mahara rereke, me panui te taiao omaoma i nga waahi papaa o ia papaa, e whakaahuatia ana i te .aocx file, ki te manatoko i nga mahi a nga punaha mahara. Heoi, ka hiahia pea koe ki te manatoko i te mahi o to Papai Ritenga me te kore e whakatinana i nga ahuatanga whakamutunga o te hoahoa papa, penei i te hoahoa i te mahere papa me te tohu i nga rohe LogicLock.

1. Manatokohia ko te haki CL_CONTEXT_COMPILER_MODE_INTELFPGA kaore i te tautuhi i to waehere kaihautu.
2. Tirotiro ki te papa/ /source/host/mmd whaiaronga o to Ritenga Ritenga.
3. Whakatuwheratia te taputapu acl_pcie_device.cpp kua mahere-mahara (MMD) file i roto i te ētita kuputuhi.
4.  Whakarerekētia te mahi reprogram i roto i te acl_pcie_device.cpp file ma te taapiri i te hokinga 0; raina, penei i raro nei:
   int ACL_PCIE_DEVICE::hōtaka anō(kore *raraunga, rahi_t raraunga_rahi)
   {
   hoki 0;
   // kapohia te kore
   int reprogram_failed = 1;
   // karekau he rbf, hash ranei i roto i te fpga.bin
   int rbf_or_hash_not_provided = 1;
   // te whakaaro karekau e rite nga hashes whakahounga turanga me te kawemai
   int hash_mismatch = 1;
   …
   }
5. Whakahiatohia te acl_pcie_device.cpp file.
6. Manatokohia ko te haki CL_CONTEXT_COMPILER_MODE_INTELFPGA kare tonu i te tautuhi.
   aro: I muri i to taapiri whakahoki 0; ki te mahi reprogram me te whakahiato i te MMD file, ka panuihia e te taiao omaoma te .aocx file me te tautapa i nga waahi papaa engari kare e whakahoahoa te FPGA. Me whakarite a ringa koe i te ahua FPGA me te .aocx file. Hei huri i tenei whanonga, tangohia te whakahoki 0; mai i te mahi reprogram me te whakahiato ano i te MMD file.

1.6. Tuhinga Tuhinga History

Rā	Putanga	Huringa
Tihema-17	2017.12.01	• I whakaingoatia CL_MEM_HETEROGENEOUS_ALTERA ki CL_MEM_HETEROGENEOUS_INTELFPGA.
Tihema-16	2016.12.13	• I whakaingoatia CL_CONTEXT_COMPILER_MODE_ALTERA ki CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Waihanga Pūnaha Mahara Heterogene ki Intel® FPGA SDK mo OpenCL
Paerewa Ritenga
Tuku Urupare
Putanga Ingarihi
Tuku Urupare
ID: 683654
Putanga: 2016.12.13

Tuhinga / Rauemi

intel Waihanga Pūnaha Mahara Heterogeneous i roto i te FPGA SDK mo OpenCL Ritenga Paerewa [pdf] Tohutohu Te Waihanga i nga Pūnaha Mahara Heterogene i roto i te FPGA SDK mo nga Papanga Ritenga OpenCL, Te Waihanga Pūnaha Mahara Heterogeneous, FPGA SDK mo nga Papanga Ritenga OpenCL

Tohutoro

• Pukapuka Kaiwhakamahi