intel MAX 10 Pūrere FPGA I runga i te UART me te Tukatuka Nios II

Nga korero hua

Ko te hoahoa tohutoro he tono ngawari e whakatinana ana i nga ahuatanga whirihoranga mamao i roto i nga punaha-a-Nios II mo nga taputapu MAX 10 FPGA. Ko te atanga UART kei roto i te MAX 10 FPGA Development Kit ka whakamahia tahi me Altera UART IP matua hei whakarato i te mahi whirihoranga mamao. Ko nga taputapu MAX10 FPGA e whakarato ana i te kaha ki te penapena kia rua nga whakaahua whirihoranga hei whakarei ake i te waahanga whakahou punaha mamao.

Whakapoto

Whakapoto	Whakaahuatanga
Avalon-MM	Avalon Memory-Mapped Configuration Flash memory
CFM	Atanga kaiwhakamahi whakairoiro
ICB	Moka Whirihoranga Arawhiti
MAP/.map	Mahere Mahara File
Nios II EDS	Nios II Tautoko Suite Hoahoa Whakauru
PFL	Whakarara Flash Loader IP matua
POF/.pof	Ahanoa Papatono File
QSPI	Tapawhā rangatū atanga peripheral
RPD/.rpd	Raraunga papatono mata
SBT	Utauta Hanga Pūmanawa
SOF/.sof	Ahanoa SRAM File
KAATA	Kaituku tukutahi/kaiwhakawhiti
UFM	Mahara flash Kaiwhakamahi

Nga Tohutohu Whakamahi Hua

Tuhinga o mua

Ko te tono o tenei hoahoa tohutoro me whai koe i te taumata o te matauranga, wheako ranei i roto i nga waahanga e whai ake nei:

Nga whakaritenga:

Ko enei e whai ake nei nga taputapu me nga taputapu rorohiko mo te hoahoa tohutoro:

Hoahoa Tohutoro Files

File Ingoa	Whakaahuatanga
Factory_image	I roto i te aratau whirihoranga whakaahua whirihoranga rua, CFM1 me CFM2 ka honoa ki te rokiroki CFM kotahi.
taupānga_whakaahua_1	Te hoahoa taputapu Quartus II file e whakakapi ana i te app_image_2 i roto i te whakamohoatanga o te punaha mamao.
taupānga_whakaahua_2	Ko te waehere tono rorohiko Nios II hei kaiwhakahaere mo te hoahoa pūnaha whakamohoa mamao.
Remote_system_upgrade.c
factory_application1.pof	Quartus II hōtaka file e ngā o te ahua wheketere me whakaahua tono 1, kia whakahoahoa ki CFM0 me CFM1 & CFM2 ia i te tuatahi stage.
factory_application1.rpd
application_image_1.rpd
application_image_2.rpd
Nios_application.pof

Ko te hoahoa tohutoro he tono ngawari e whakatinana ana i nga ahuatanga whirihoranga mamao i roto i nga punaha-a-Nios II mo nga taputapu MAX 10 FPGA. Ko te atanga UART kei roto i te MAX 10 FPGA Development Kit ka whakamahia tahi me Altera UART IP matua ki te whakarato i te mahi whirihoranga mamao.

Nga korero e pa ana

Hoahoa Tohutoro Files

Whakamohoa Pūnaha Mamao me te MAX 10 FPGA Neke atuview

Ma te ahuatanga whakamohoatanga o te punaha mamao, ka taea te mahi i nga whakapainga me te whakatika iro mo nga taputapu FPGA. I roto i te taiao o te punaha whakauru, me whakahōu i nga wa katoa mo nga momo kawa, penei i te UART, Ethernet, me I2C. Ina whakaurua he FPGA i roto i te punaha whakauru, ka taea e nga whakahoutanga firmware te whakauru i nga whakahoutanga o te ahua taputapu i runga i te FPGA.
Ko nga taputapu MAX10 FPGA e whakarato ana i te kaha ki te penapena kia rua nga whakaahua whirihoranga hei whakarei ake i te waahanga whakahou punaha mamao. Ko tetahi o nga whakaahua ko te ahua o muri ka utaina mena ka puta he hapa ki te ahua o naianei.

Whakapoto

Ripanga 1: Rarangi Whakapoto

Whakaahuatanga Whakapoto
Avalon-MM	Mahara Avalon-Mahere
CFM	Pumahara kohiko whirihoranga
GUI	Atanga kaiwhakamahi whakairoiro
ICB	Moka Whirihoranga Arawhiti
MAP/.map	Mahere Mahara File
Nios II EDS	Nios II Tautoko Suite Hoahoa Whakauru
PFL	Whakarara Flash Loader IP matua
POF/.pof	Ahanoa Papatono File

• Intel Corporation. Katoa nga mana. Intel, te Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus me Stratix kupu me nga waitohu he tohu tohu na Intel Corporation me ona apiti i te US me etahi atu whenua. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei.
• Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

Tuhinga o mua

Whakapoto QSPI	Whakaahuatanga Tapawhā rangatū atanga peripheral
RPD/.rpd	Raraunga papatono mata
SBT	Utauta Hanga Pūmanawa
SOF/.sof	Ahanoa SRAM File
UART	Kaituku tukutahi/kaiwhakawhiti
UFM	Mahara flash Kaiwhakamahi

Tuhinga o mua

• Ko te tono o tenei hoahoa tohutoro me whai koe i te taumata o te matauranga, wheako ranei i roto i nga waahanga e whai ake nei:
• Te matauranga mahi mo nga punaha Nios II me nga taputapu hei hanga. Kei roto i enei punaha me nga taputapu te rorohiko Quartus® II, Qsys, me te Nios II EDS.
• Te mohiotanga mo nga tikanga whirihoranga Intel FPGA me nga taputapu, penei i te MAX 10 FPGA whirihoranga o roto, te waahanga whakamohoatanga punaha mamao me te PFL.

Nga whakaritenga

• Ko enei e whai ake nei nga taputapu me nga taputapu rorohiko mo te hoahoa tohutoro:
• MAX 10 FPGA kete whanaketanga
• Quartus II putanga 15.0 me Nios II EDS
• He rorohiko me te taraiwa UART mahi me te atanga
• Tetahi ā-rua/haukauono file ētita

Hoahoa Tohutoro Files

Ripanga 2: Hoahoa Files Kei roto i te Hoahoa Tohutoro

File Ingoa Factory_image	Whakaahuatanga • Te hoahoa taputapu Quartus II file kia penapena ki CFM0. • Ko te ahua whakamuri/whakaahua wheketere ka whakamahia ina puta te hapa i te tango whakaahua tono.
taupānga_whakaahua_1	• Te hoahoa taputapu Quartus II file kia penapena ki CFM1 me CFM2.(1) • Ko te whakaahua tono tuatahi i utaina ki te taputapu.

1. I roto i te aratau whirihoranga whakaahua whirihoranga rua, ka honoa te CFM1 me te CFM2 ki te rokiroki CFM kotahi.

File Ingoa taupānga_whakaahua_2	Whakaahuatanga Te hoahoa taputapu Quartus II file ka whakakapi i te app_image_2 i te wa whakamohoatanga o te punaha mamao.
Mamao_system_ upgrade.c	Ko te waehere tono rorohiko Nios II hei kaiwhakahaere mo te hoahoa punaha whakamohoatanga mamao.
Mamao Terminal.exe	• Ka taea te whakahaere file me te GUI. • Ka noho hei tauranga mo te kaihautu ki te mahi tahi me te kete whanaketanga MAX 10 FPGA. • Ka tuku raraunga hotaka ma te UART. • Kua whakauruhia te waehere puna mo tenei tauranga.

Ripanga 3: Kaiwhakaako Files Kei roto i te Hoahoa Tohutoro

Ka taea e koe te whakamahi i enei rangatira files mo te hoahoa tohutoro me te kore e whakahiato i te hoahoa files.

File Ingoa   factory_application1.pof factory_application1.rpd	Whakaahuatanga Quartus II hōtaka file kei roto ko te ahua wheketere me te whakaahua tono 1, ka whakahoahoa ki te CFM0 me te CFM1 & CFM2 i te timatanga.tage.
factory_application2.pof factory_application2.rpd	• Ko te kaupapa Quartus II file kei roto ko te ahua wheketere me te ahua tono 2. • Ko te ahua tono 2 ka tangohia i muri mai hei whakakapi i te ahua tono 1 i te wa o te whakamohoatanga o te punaha mamao, ko te ingoa application_ image_2.rpd kei raro nei.
application_image_1.rpd	Quartus II nga raraunga hotaka mata file kei roto te ahua tono 1 anake.
application_image_2.rpd	Quartus II nga raraunga hotaka mata file kei roto te ahua tono 2 anake.
Nios_application.pof	• Papatonotanga file kei roto ko Nios II tukatuka rorohiko tono .hex file anake. • Kia whakahoahoa ki te rama QSPI waho.
pfl.sof	• Quartus II .sof kei roto PFL. • Whakatakahia ki te rama QSPI i runga MAX 10 FPGA kete Whanaketanga.

Whakaahuatanga Mahi Hoahoa Tohutoro

Nios II Gen2 Tukatuka

• Ko te Tukatuka Nios II Gen2 i roto i te hoahoa tohutoro e whai ake nei nga mahi:
• He rangatira pahi e whakahaere ana i nga mahi atanga katoa me te Altera On-Chip Flash IP matua tae atu ki te panui, te tuhi, me te ūkui.
• Ka whakarato i te algorithm i roto i te rorohiko ki te tango i te awa moka hotaka mai i te rorohiko kaihautu me te whakaoho i te whirihora ano ma te matua IP Whirihoranga Takirua.
• Me whakarite e koe te vector tautuhi o te tukatuka. Ko tenei hei whakarite kia mauhia e te kaitukatuka te waehere tono tika mai i te UFM, te uira QSPI waho ranei.
• Tuhipoka: Mena he nui te waehere tono Nios II, ka kii a Intel kia penapenahia e koe te waehere tono ki te rama QSPI o waho. I roto i tenei hoahoa tohutoro, kei te tohu te vector tautuhi ki te rama QSPI waho kei te rongoa te waehere tono Nios II.

Nga korero e pa ana

• Nios II Gen2 Whakawhanakenga Maama Whakaakoranga
• Ka whakarato i etahi atu korero mo te whakawhanake i te Tukatuka Nios II Gen2.

Altera On-Chip Flash IP Core

• Ko te Altera On-Chip Flash IP matua he atanga mo te tukatuka Nios II ki te mahi panui, tuhi, whakakore ranei i nga mahi ki te CFM me te UFM. Ko te Altera On-Chip Flash IP matua e whakarato ana ka taea e koe te uru, te whakakore me te whakahou i te CFM me te awa moka whirihoranga hou. Ko te ētita tawhā Altera On-Chip Flash IP e whakaatu ana i te awhe wāhitau kua whakaritea mo ia wahanga mahara.

Nga korero e pa ana

• Altera On-Chip Flash IP Core
• Ka whakarato i etahi atu korero mo Altera On-Chip Flash IP Core.

Altera Tärua Whirihoranga IP Core

• Ka taea e koe te whakamahi i te Altera Dual Configuration IP matua ki te uru atu ki te poraka whakamohoa punaha mamao i roto i nga taputapu MAX 10 FPGA. Ko te Altera Dual Configuration IP matua ka taea e koe te whakaoho i te whirihora ano ina oti te tango i te ahua hou.

Nga korero e pa ana

• Altera Tärua Whirihoranga IP Core
• Ka whakarato i etahi atu korero mo Altera Dual Configuration IP Core

Altera UART IP Core

• Ka taea e te UART IP matua te whakawhiti korero o nga rerenga korero rangatū i waenga i te punaha whakauru i roto i te MAX 10 FPGA me tetahi taputapu o waho. Hei rangatira Avalon-MM, ka whakawhitiwhiti te tukatuka Nios II me te UART IP matua, he pononga Avalon-MM. Ka mahia tenei korero ma te panui me te tuhi i te mana whakahaere me nga rehita raraunga.
• Ka whakatinanahia e te matua te wa kawa RS-232 me te whakarato i nga ahuatanga e whai ake nei:
• reeti baud ka taea te whakarite, te parite, te aukati, me nga moka raraunga
• tohu tohu whakahaere rere RTS/CTS

Nga korero e pa ana

• UART Core
• Ka whakarato i etahi atu korero mo te UART Core.

Paetukutuku Quad SPI Kaiwhakahaere IP Core

• Ko te Generic Quad SPI Controller IP matua e mahi ana hei atanga i waenga i te MAX 10 FPGA, te uira o waho me te uira QSPI i runga i te poari. Ko te matua te uru ki te QSPI flash ma te panui, te tuhi me te whakakore i nga mahi.
  A, no te whakawhānui i te tono Nios II ki atu tohutohu, te file te rahi o te hex file i hangaia mai i te tono Nios II ka nui ake. I tua atu i tetahi tepe rahi, karekau te UFM e whai waahi rawaka hei penapena i te hex tono file. Hei whakaoti i tenei, ka taea e koe te whakamahi i te rama QSPI o waho e waatea ana i runga i te kete Whakawhanake MAX 10 FPGA hei penapena i te hex tono. file.

Ko te Nios II EDS Software Application Design

• Kei roto i te hoahoa tohutoro te waehere tono rorohiko Nios II e whakahaere ana i te hoahoa punaha whakamohoa mamao. Ka whakautu te waehere tono rorohiko Nios II ki te tauranga kaihautu ma te UART ma te whakamahi i nga tohutohu motuhake.

Whakahōu Atahanga Taupānga Mamao

• Whai muri i to tuku i tetahi awa moka papatono file ma te whakamahi i te Kapeka Mamao, kua hoahoatia te tono rorohiko Nios II hei mahi e whai ake nei:

1. Whakaritea te Altera On-Chip Flash IP matua Mana Rēhita kia kore e parea te rāngai CFM1 & 2.
2. Whakahaerehia nga mahi whakakore rangai ki CFM1 me CFM2. Ka pootihia e te raupaparorohiko te rehita mana o te Altera On-Chip Flash IP matua kia tutuki pai ai te whakakore.
3. Whiwhi 4 paita o te awa moka i te wa mai i stdin. Ka taea te whakamahi i te whakauru me te putanga paerewa ki te tiki raraunga mai i te tauranga kaihautu me te whakaputa putanga ki runga. Ko nga momo whakaurunga paerewa me te kowhiringa putanga ka taea te whakarite ma te BSP Editor i roto i te taputapu Nios II Eclipse Build.
4. Whakahokia te raupapa moka mo ia paita.
   • Tuhipoka: Na te whirihoranga o Altera On-Chip Flash IP Core, me huri nga paita katoa o nga raraunga i mua i te tuhi ki te CFM.
5. Tīmatahia te tuhi 4 paita o te raraunga i te wa kotahi ki CFM1 me CFM2. Ka haere tonu tenei tukanga tae noa ki te mutunga o te awa moka papatono.
6. Pootihia te rehita mana o Altera On-Chip Flash IP kia pai ai te mahi tuhi. Tohua he karere hei tohu kua oti te tuku.
   • Tuhipoka: Ki te rahua te mahi tuhi, ka whakamutua e te tauranga te tuku awa moka ka puta he karere hapa.
7. Ka tautuhi i te Rēhita Mana ki te tiaki ano i te CFM1 me te CFM2 hei aukati i nga mahi tuhi kore.

Nga korero e pa ana

• pof Whakatupuranga na roto i te Whakatahuri Papatonotanga Filekei runga
• He tuku korero mo te hanga rpd files i te wa o te whakarereke i nga papatono files.

Te Whakatairanga Anō Mamao

• I muri i to kowhiri i te mahi whirihora hou i te Kapeka Mamao kaihautu, ka mahia e te tono rorohiko Nios II enei e whai ake nei:

1. Whiwhi i te whakahau mai i te whakaurunga paerewa.
2. Tīmatahia te whirihora anō me ngā mahi tuhi e rua e whai ake nei:

• Tuhia te 0x03 ki te wāhitau wāhikē o 0x01 i roto i te matua IP Whirihoranga Takirua. Ko tenei mahi ka tuhirua i te titi CONFIG_SEL tinana ka whakatauhia te Atahanga 1 hei ahua whirihoranga whawhai.
• Tuhia te 0x01 ki te wāhitau wāhikē o 0x00 i te matua IP Whirihoranga Takirua. Ma tenei mahi ka whirihora ano ki te ahua tono i CFM1 me CFM2

Tohutoro Hoahoa Whakaaturanga

Hanga Papatonotanga Files

• Me whakaputa e koe te kaupapa e whai ake nei files i mua i te kaha ki te whakamahi i te whakamohoatanga punaha mamao i runga i te kete Whakawhanake MAX 10 FPGA:

Mo te QSPI Papatonotanga:

• sof—whakamahi te pfl.sof kei roto i te hoahoa tohutoro ka taea ranei e koe te whiriwhiri ki te hanga i tetahi .sof rereke kei roto i a koe ake hoahoa PFL
• pof—whirihora file he mea hanga mai i te .hex me te whakahoahoa ki te uira QSPI.
• Mo Whakapai Pūnaha mamao:
• pof—whirihora file he mea hanga mai i te .sof me te whakamaarama ki te kohiko o roto.
• rpd—kei roto nga raraunga mo te rama o roto kei roto nga tautuhinga ICB, CFM0, CFM1 me UFM.
• mahere—mau te wahitau mo ia wahanga mahara o nga tautuhinga ICB, CFM0, CFM1 me UFM.

Te whakaputa files mo te QSPI Programming

Hei whakaputa i te .pof file mo te kaupapa QSPI, mahia nga mahi e whai ake nei:

1. Hangaia te Kaupapa Nios II me te whakaputa HEX file.
   • Tuhipoka: Tirohia AN730: Nga Tikanga Whakaoho Tukatuka Nios II I roto i nga taputapu MAX 10 mo nga korero mo te hanga kaupapa Nios II me te whakaputa HEX file.
2. I runga i te File tahua, pāwhiri Tahuri Papatonotanga Files.
3. I raro i te Hotaka Huaputa file, tohua te Ahanoa Papatono File (.pof) i roto i te Papatonotanga file rarangi momo.
4. I roto i te rarangi Aratau, tohua 1-bit Passive Serial.
5. I te rarangi taputapu Whirihoranga, tohua CFI_512Mb.
6. I roto i te File pouaka ingoa, whakapūtā te file ingoa mo te kaupapa file kei te hiahia koe ki te hanga.
7. I roto i te Whakauru files ki te huri i te rarangi, tango i nga Kōwhiringa me te rarangi raraunga SOF. Patohia te Tāpiri Raraunga Hex ka puta he pouaka korero Tāpiri Raraunga Hex. I roto i te pouaka Tāpiri Raraunga Hex, tīpakohia te Whakatau Whakataunga me te whakauru i te .hex file i hangaia mai i Nios II EDS Build Tools.
8. Kia oti nga tautuhinga katoa, pawhiria te Hanga ki te whakaputa i nga kaupapa e pa ana file.

Nga korero e pa ana

AN730: Nga Tikanga Whakaoho Tukatuka Nios II I MAX 10 Pūrere FPGA
Te whakaputa files mo te Whakahoutanga Pūnaha Mamao

Hei whakaputa i te .pof, .map me te .rpd files mo te whakahou i te punaha mamao, mahia nga mahi e whai ake nei:

1. Whakahokia te Factory_image, application_image_1 me application_image_2, ka whakahiato i nga hoahoa e toru.
2. Hangaia kia rua .pof files whakaahuatia i roto i te ripanga e whai ake nei:
   • Tuhipoka: Tirohia te .pof Generation na roto i te Papatono Tahuri Files mo nga taahiraa mo te whakaputa .pof files.
3. Whakatuwheratia te app2.rpd ma te whakamahi i tetahi ētita hex.
4. I roto i te ētita hex, tīpakohia te paraka raraunga ā-rua i runga i te tiimata me te mutunga o te waahi ma te tohu ki te .map file. Ko te tiimata me te mutunga mo te taputapu 10M50 ko te 0x12000 me te 0xB9FFF. Tāruatia tēnei paraka ki tētahi hōu file ka tiakina ki tetahi .rpd rereke file. Ko tenei .rpd hou file he whakaahua tono 2 anake.

pof Whakatupuranga na roto i te Whakatahuri Papatonotanga Files

Hei huri i te .sof files ki .pof files, whai i enei mahi:

1. I runga i te File tahua, pāwhiri Tahuri Papatonotanga Files.
2. I raro i te Hotaka Huaputa file, tohua te Ahanoa Papatono File (.pof) i roto i te Papatonotanga file rarangi momo.
3. I roto i te Aratau rārangi, tīpako Whirihoranga-roto.
4. I roto i te File pouaka ingoa, whakapūtā te file ingoa mo te kaupapa file kei te hiahia koe ki te hanga.
5. Hei whakaputa Mahere Mahara File (.map), whakakā Waihanga Mahere Mahara File (Whakaputa aunoa_file.mapi). Kei roto i te .map te wahitau o te CFM me te UFM me te whakatakotoranga ICB i tautuhia e koe i roto i te waahanga Option/Boot Info.
6.  Hei whakaputa Raw Papatonotanga Raraunga (.rpd), whakakā Waihanga raraunga whirihora RPD (Hanga putanga_file_auto.rpd).
   Ma te Mahere Mahara File, ka taea e koe te tautuhi i nga raraunga mo ia poraka mahi i roto i te .rpd file. Ka taea hoki e koe te tango i nga raraunga uira mo nga taputapu hotaka tuatoru, whakahou ranei i te whirihoranga, raraunga kaiwhakamahi ranei ma te Altera On-Chip Flash IP.
7. Ka taea te taapiri te .sof ma te Whakauru files ki te tahuri rārangi a ka taea e koe te tāpiri ake ki te rua .sof files.
   • Mo nga kaupapa whakamohoatanga punaha mamao, ka taea e koe te pupuri i nga raraunga wharangi 0 taketake ki te .pof, me te whakakapi i nga raraunga wharangi 1 ki te .sof hou. file. Hei mahi i tenei, me whakauru koe i te .pof file kei te wharangi 0, katahi
     tāpirihia te whārangi .sof, kātahi ka tāpirihia te .sof hou file ki
8. Kia oti nga tautuhinga katoa, pawhiria te Hanga ki te whakaputa i nga kaupapa e pa ana file.

Te whakahoahoa i te QSPI

Hei whakarite i te waehere tono Nios II ki te QSPI flash, mahia nga mahi e whai ake nei:

1. I runga i te Kete Whakawhanaketanga MAX 10 FPGA, huri te MAX10_BYPASSn ki te 0 ki te karo i te taputapu VTAP (MAX II) i runga i te papa.
2. Honoa te Intel FPGA Download Cable (USB Blaster i mua) ki te JTAG pane.
3. I roto i te matapihi Papatono, pawhiria te Tatūnga Pūmārō ka kōwhiri i te USB Blaster.
4. I roto i te Aratau rārangi, tīpako JTAG.
5. Patohia te patene Rapu Aunoa i te taha maui.
6. Tīpakohia te taputapu kia hotaka, ka paato i te Tāpiri File.
7. Tīpakohia te pfl.sof.
8. Patohia te Tīmata ki te tīmata i te hōtaka.
9. I muri i te angitu o te hotaka, me te kore e whakawetohia te poari, paato ano te paatene Tirohanga Aunoa i te taha maui. Ka kite koe i te kohiko QSPI_512Mb ka puta ki te matapihi hötaka.
10. Tīpakohia te taputapu QSPI, ka paato Tāpiri File.
11. Tīpakohia te .pof file i hangaia i mua mai i te .hex file.
12. Patohia te Tīmata kia timata te whakahoahoa i te kohiko QSPI.

Te whakamaoritanga i te FPGA me te Whakaahua Tuatahi ma te whakamahi i a JTAG

Me whakarite e koe te app1.pof ki te FPGA hei ahua tuatahi o te taputapu. Hei whakarite i te app1.pof ki te FPGA, mahia nga mahi e whai ake nei:

1. I roto i te matapihi Papatono, pawhiria te Tatūnga Pūmārō ka kōwhiri i te USB Blaster.
2. I roto i te Aratau rārangi, tīpako JTAG.
3. Patohia te patene Rapu Aunoa i te taha maui.
4. Tīpakohia te taputapu kia hotaka, ka paato i te Tāpiri File.
5. Tīpakohia te app1.pof.
6. Patohia te Tīmata ki te tīmata i te hōtaka.

Te Whakahou Atahanga me te Whakaoho Whakahoutanga ma te whakamahi i te UART

Hei whirihora mamao i to kete whanaketanga MAX10 FPGA, mahia nga mahi e whai ake nei:

1. Tuhipoka: I mua i to tiimata, me whakarite nga mea e whai ake nei:
   • kua tautuhia te pine CONFIG_SEL ki te 0
   • kua hono te tauranga UART o to papa ki to rorohiko
   • Whakatuwherahia te Terminal.exe Mamao ka tuwhera te atanga Kapeka Mamao.
2. Pāwhiritia Tautuhinga ka puta te matapihi tautuhinga tauranga rangatū.
3. Tautuhia nga tawhā o te tauranga mamao kia rite ki nga tautuhinga UART i tohua ki te Quartus II UART IP matua. Kia oti te tautuhinga, pawhiria OK.
4. Pēhia te pātene nCONFIG ki te kete whanaketanga, ki te kī-i roto 1 ranei i roto i te pouaka kuputuhi Tukua, ka paato i te Enter.
   • Ka puta he rarangi o nga whiringa mahi i runga i te tauranga, penei i raro nei:
   • Tuhipoka: Hei whiriwhiri i tetahi mahi, paatohia te nama ki te pouaka kuputuhi Tukua, ka paato i te Whakauru.
5. Hei whakahou i te ahua tono 1 me te ahua tono 2, tohua te mahi 2. Ka akiakihia koe ki te whakauru i te wahitau timatanga me te mutunga o CFM1 me CFM2.
   • Tuhipoka: Ko te wahitau kua whakaatuhia ki te mapi file kei roto nga tautuhinga ICB, CFM me te UFM engari ko te Altera On-Chip
   • Ka taea e Flash IP te uru ki te CFM me te UFM anake. No reira, he waahi waahi kei waenganui i te wahitau kua whakaatuhia ki te mapi file me Altera On-Chip Flash IP matapihi tawhā.
6. Whakauruhia te wahitau i runga i te wahitau kua tohua e te Altera On-Chip Flash IP tawhā matapihi.
   • Ka timata aunoa te whakakore i muri i to urunga ki te wahitau mutunga.
7. I muri i te angitu o te whakakore, ka akiakihia koe ki te whakauru i te kaupapa .rpd file mo te whakaahua tono 2.
   • Hei tuku ake i te ahua, pawhiria te TukuaFile te paatene, ka kowhiria te .rpd kei roto te ahua tono 2 anake ka paatoo Tuwhera.
   • Tuhipoka: I tua atu i te ahua tono 2, ka taea e koe te whakamahi i tetahi ahua hou e hiahia ana koe ki te whakahou ki te taputapu.
   • Ka tiimata tika te mahi whakahou ka taea e koe te aro turuki i te ahunga whakamua ma te tauranga. Ka tohu te tahua mahi kua oti ka taea e koe te kowhiri i te mahi ka whai ake.
8. Hei whakaoho i te whirihora, tohua te mahi 4. Ka taea e koe te kite i te whanonga LED e tohu ana i te ahua rereke kua utaina ki roto i te taputapu.

Whakaahua	Tūnga LED (Hakaheke Hohe)
Whakaahua wheketere	01010
Whakaahua Taupānga 1	10101
Whakaahua Taupānga 2	01110

Tuhinga o mua Tuhinga

Rā	Putanga	Huringa
Hui-tanguru 2017	2017.02.21	I whakaingoatia ano ko Intel.
Pipiri 2015	2015.06.15	Tukunga tuatahi.

Tuhinga / Rauemi

intel MAX 10 Pūrere FPGA I runga i te UART me te Tukatuka Nios II [pdf] Aratohu Kaiwhakamahi MAX 10 Pūrere FPGA Neke atu i te UART me te Nios II Tukatuka, MAX 10 FPGA Pūrere, Neke atu i te UART me te Nios II Tukatuka, Neke atu i te UART, Nios II Tukatuka UART, Nios II, Tukatuka UART

Tohutoro

• Pukapuka Kaiwhakamahi