SmartFusion2 MSS
Whirihoranga Kaiwhakahaere DDR
Libero SoC v11.6 me muri mai 

Kupu Whakataki

Ko te SmartFusion2 MSS he kaiwhakahaere DDR whakauru. Ko tenei kaiwhakahaere DDR te tikanga ki te whakahaere i te mahara DDR kore maramara. Ka taea te uru atu ki te kaiwhakahaere MDDR mai i te MSS tae atu ki te papanga FPGA. I tua atu, ka taea hoki te whakakore i te kaiwhakahaere DDR, me te whakarato i tetahi atanga taapiri ki te papanga FPGA (Aratau Kaiwhakahaere ngawari (SMC)).
Hei whirihora katoa i te kaiwhakahaere MSS DDR, me:

1. Tīpakohia te ara raraunga ma te whakamahi i te MDDR Configurator.
2. Tautuhia nga uara rehita mo nga rehita kaiwhakahaere DDR.
3. Tīpakohia nga iarere karaka mahara DDR me te papanga FPGA ki te ōwehenga karaka MDDR (mehemea e hiahiatia ana) ma te whakamahi i te MSS CCC Configurator.
4. Tūhonohia te atanga whirihoranga APB o te pūmana i tautuhia e te otinga Whakakotahitanga Peripheral. Mo te ara iahiko Arawhiti MDDR i hangaia e te Kaihanga Pūnaha, tirohia te "Ara Whirihora MSS DDR" kei te wharangi 13 me te Whakaahua 2-7.
   Ka taea hoki e koe te hanga i a koe ake ara iahiko arawhiti ma te whakamahi mokemoke (ehara i te Kaihanga Pūnaha) Te Arataki Piko. Tirohia te SmartFusion2 Standalone Peripheral Initialization Aratohu Kaiwhakamahi.

MDDR Whirihoranga

Ka whakamahia te MDDR Configurator ki te whirihora i te ara raraunga whanui me nga Tawhā Mahara DDR waho mo te kaiwhakahaere MSS DDR.

Ko te ripa Whānui e whakatakoto ana i o tautuhinga Atanga Mahara me te papanga (Whakaahua 1-1).
Tautuhinga Mahara
Whakauruhia te wa Whakatau Mahara DDR. Koinei te wa e hiahia ana te mahara DDR ki te arawhiti. Ko te uara taunoa ko te 200 tatou. Tirohia to Rau Raraunga Mahara DDR mo te uara tika hei whakauru.
Whakamahia nga Tautuhinga Mahara hei whirihora i o whiringa mahara ki te MDDR.

• Momo Mahara - LPDDR, DDR2, DDR3 ranei
• Whānui Raraunga – 32-bit, 16-bit, 8-bit ranei
• SECDED Whakahohea ECC – ON, OFF ranei
• Kaupapa Apitireihana – Momo-0, Momo -1, Momo-2, Momo-3
• Tautuhinga Manaakitanga Rawa - Ko nga uara whaimana mai i te 0 ki te 15
• Whānui Wāhitau (moka) – Tirohia to Pepa Raraunga Mahara DDR mo te maha o nga rarangi rarangi, peeke, me nga moka wahitau pou mo te mahara LPDDR/DDR2/DDR3 e whakamahia ana e koe. tīpakohia te tahua kume-iho hei whiriwhiri i te uara tika mo nga rarangi/peeke/tīwae kia rite ki te pepa raraunga o te mahara LPDDR/DDR2/DDR3.

Tuhipoka: Ko te nama kei roto i te rarangi kume-iho e tohu ana ki te maha o nga moka Wāhitau, kaua ki te maha o nga rarangi/peeke/tīwae. Mo te exampKi te mea e 4 nga peeke o to mahara DDR, tohua te 2 (2 ²=4) mo nga peeke. Mena he 8 nga peeke o to mahara DDR, tohua te 3 (2³ =8) mo nga peeke.

Tautuhinga Atanga papanga
Ma te taunoa, kua whakaritea te tukatuka Cortex-M3 pakeke kia uru atu ki te Kaiwhakahaere DDR. Ka taea hoki e koe te tuku i tetahi Kaiwhakaako papanga kia uru ki te Kaiwhakahaere DDR ma te whakahohe i te pouakataki Tautuhinga Atanga papanga. I tenei keehi, ka taea e koe te whiriwhiri i tetahi o nga whiringa e whai ake nei:

• Whakamahia he Atanga AXI - Ka uru te Kaiwhakaako papanga ki te Kaiwhakahaere DDR na roto i te atanga AXI 64-bit.
• Whakamahia he Atanga AHBLite Kotahi - Ka uru te Kaiwhakaako papanga ki te Kaiwhakahaere DDR ma te atanga AHB 32-bit kotahi.
• Whakamahia nga Atanga AHBLite e rua - E rua nga Kaiwhakaako papanga ka uru ki te Kaiwhakahaere DDR ma te whakamahi i nga atanga AHB 32-bit e rua.
  Te whirihoranga view (Whakaahua 1-1) nga whakahou i runga i to whiringa Atanga papanga.

Te Kaha Puku I/O (DDR2 me DDR3 anake)
Tīpakohia tetahi o nga kaha puku e whai ake nei mo o DDR I/Os:

• Haurua Puku Kaha
•  Kaha Puku Katoa

Ka whakatakotohia e Libero SoC te Paerewa DDR I/O mo to punaha MDDR i runga i to momo Mahara DDR me te Kaha Puku I/O (e whakaatu ana i te Ripa 1-1).
Ripanga 1-1 • Te Kaha Puku I/O me te Momo Mahara DDR

Momo Mahara DDR	Puku Kaha Haurua	Puku Kaha Katoa
DDR3	SSTL15I	SSTL15II
DDR2	SSTL18I	SSTL18II
LPDDR	LPDRI	LPDRII

Paerewa IO (LPDDR anake)
Tīpakohia tētahi o ngā kōwhiringa e whai ake nei:

• LVCMOS18 (Te Mana Rawa) mo te paerewa LVCMOS 1.8V IO. Ka whakamahia i roto i nga tono LPDDR1 angamaheni.
• LPDDRI Tuhipoka: I mua i to kowhiri i tenei paerewa, me mohio kei te tautoko to poari i tenei paerewa. Me whakamahi koe i tenei whiringa ka aro ki te M2S-EVAL-KIT, ki nga papa SF2-STARTER-KIT ranei. Ko nga paerewa LPDDRI IO e hiahia ana kia whakauruhia he parenga IMP_CALIB ki runga i te papa.

IO Whakatikatika (LPDDR anake)
Whiriwhiria tetahi o nga whiringa e whai ake nei ina whakamahi ana koe i te paerewa LVCMOS18 IO:

• On
• Weto (Momo)

Ko te Whakatairanga ON me te OFF ka taea te whakahaere i te whakamahi i te paraka whakatika IO e whakatika ana i nga taraiwa IO ki tetahi parenga o waho. Ina OFF, ka whakamahia e te taputapu he whakatikanga taraiwa IO.
Ina ON, me whakauru he parenga IMP_CALIB 150-ohm ki runga i te PCB.
Ka whakamahia tenei ki te whakatikatika i te IO ki nga ahuatanga PCB. Heoi, ka taatuhia ki te ON, me whakauru he parenga, karekau ranei te kaiwhakahaere mahara e arawhiti.
Mo etahi atu korero, tirohia te AC393-SmartFusion2 me IGLOO2 Poari Hoahoa Aratohu Tono
Tuhipoka me te SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces Aratohu Kaiwhakamahi.

Whirihoranga Kaiwhakahaere MDDR

Ina whakamahi koe i te Kaiwhakahaere MSS DDR ki te uru atu ki tetahi Mahara DDR o waho, me whirihora te Kaiwhakahaere DDR i te wa whakahaere. Ka mahia tenei ma te tuhi i nga raraunga whirihoranga ki nga rehita whirihoranga kaiwhakahaere DDR i whakatapua. Ko tenei raraunga whirihoranga kei te whakawhirinaki ki nga ahuatanga o te mahara DDR o waho me to tono. Ko tenei waahanga e whakaatu ana me pehea te whakauru i enei tawhā whirihoranga i roto i te whirihora kaiwhakahaere MSS DDR me pehea te whakahaerenga o nga raraunga whirihoranga hei waahanga o te otinga Whakawhitinga Mokowhiti katoa.

Nga Rēhita Mana MSS DDR
Ko te Kaiwhakahaere MSS DDR he huinga rehita e tika ana kia whirihora i te wa whakahaere. Ko nga uara whirihoranga mo enei rehita e whakaatu ana i nga tawhā rereke, penei i te aratau DDR, te whanui PHY, te aratau pakaru, me te ECC. Mo nga taipitopito katoa mo nga rehita whirihoranga a te kaiwhakahaere DDR, tirohia te SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces Aratohu Kaiwhakamahi.
MDDR Rēhita Whirihoranga
Whakamahia nga ripa Whakakotahitanga Mahara (Whakaahua 2-1, Whakaahua 2-2, me te Whakaaturanga 2-3) me te Wa Maharahara (Whakaahua 2-4) hei whakauru i nga tawhā e rite ana ki to Mahara DDR me to tono. Ko nga uara ka whakauruhia e koe ki enei ripa ka whakamaoritia aunoa ki nga uara rehita e tika ana. Ina pawhiria e koe tetahi tawhā motuhake, ka whakaahuahia tana rehita e rite ana ki te pihanga Whakaahuatanga Rēhita (te wahanga o raro i te Whakaahua 1-1 i te wharangi 4).
Te Maharahara Arawhiti
Ko te ripa Whakaara Mahara ka taea e koe te whirihora i nga huarahi e hiahia ana koe kia arawhitia o mahara LPDDR/DDR2/DDR3. He rereke te tahua me nga whiringa e waatea ana i te ripa Whakaoho Mahara ki te momo mahara DDR (LPDDR/DDR2/DDR3) e whakamahia ana e koe. Tirohia to Rau Raraunga Mahara DDR ina whirihora e koe nga whiringa. Ina huri koe, ka whakauru ranei i tetahi uara, ka hoatu e te pihanga Whakaahuatanga Rēhita te ingoa rehita me te uara rehita kua whakahoutia. Ko nga uara muhu ka kara hei whakatupato. Ko te ahua 2-1, ko te Whakaahua 2-2, me te Whakaaturanga 2-3 e whakaatu ana i te ripa Whakawhitinga mo te LPDDR, DDR2 me DDR3.

• Aratau Wā – Tīpakohia te aratau 1T, 2T rānei. I roto i te 1T (te aratau taunoa), ka taea e te kaiwhakahaere DDR te tuku whakahau hou mo ia huringa karaka. I roto i te aratau wa 2T, ka mau te kaiwhakahaere DDR te wahitau me te pahi whakahau e tika ana mo nga huringa karaka e rua. Ka whakaitihia te kaha o te pahi ki te whakahau kotahi mo ia karaka e rua, engari ka ruarua te nui o te tatūnga me te wa pupuri.
• Huanga-Waahanga Tāmata Whaiaro (LPDDR anake). Ko tenei ahuatanga mo te penapena hiko mo te LPDDR.
  Tīpakohia tetahi o enei e whai ake nei mo te kaiwhakahaere ki te whakahou i te nui o te mahara i te wa o te whakahou whaiaro:
  – Te huinga katoa: Peeke 0, 1,2, me te 3
  – Haurua huinga: Peeke 0 me 1
  – Raupapa hauwhā: Peeke 0
  – Kotahi-waru nga rarangi: Peeke 0 me te wahitau rarangi MSB=0
  – Kotahi-tekau ma ono nga rarangi: Peeke 0 me te wahitau rarangi MSB me MSB-1 e rite ana ki te 0.
  Mo etahi atu whiringa, tirohia to Pepa Raraunga Mahara DDR ina whirihora e koe nga whiringa.
  

Te Wa Mahara
Ma tenei ripa ka taea e koe te whirihora i nga tawhā Mahara Wā. Tirohia te Pepa Raraunga o to mahara LPDDR/ DDR2/DDR3 i te wa e whirihora ana i nga tawhā Wā Mahara.
Ina huri koe, ka whakauru ranei i tetahi uara, ka hoatu e te pihanga Whakaahuatanga Rēhita te ingoa rehita me te uara rehita kua whakahoutia. Ko nga uara muhu ka kara hei whakatupato.

Te kawemai i te Whirihoranga DDR Files
I tua atu i te whakauru i nga tawhā Mahara DDR ma te whakamahi i nga ripa Whakakotahitanga Mahara me te Wā, ka taea e koe te kawemai i nga uara rehita DDR mai i te file. Ki te mahi pera, pawhiria te paatene Whirihoranga Kawemai ka whakatere ki te tuhinga file kei roto nga ingoa rehita DDR me nga uara. Ko te ahua 2-5 e whakaatu ana i te wetereo whirihoranga kawemai.

Tuhipoka: Mena ka whiriwhiri koe ki te kawemai i nga uara rehita kaore i te whakauru ma te whakamahi i te GUI, me tohu e koe nga uara rehita katoa e tika ana. Tirohia te SmartFusion2 SoC FPGA High Speed ​​DDR Interfaces Aratohu Kaiwhakamahi mo nga taipitopito.

Kaweake i te Whirihoranga DDR Files
Ka taea hoki te kaweake i nga raraunga whirihoranga rehita o naianei ki roto i te tuhinga file. Tenei file kei roto i nga uara rehita i kawemai e koe (mehemea he) me era i tatauhia mai i nga tawhā GUI i whakauruhia e koe ki tenei korero.
Mena kei te pirangi koe ki te wete i nga huringa i mahia e koe ki te whirihoranga rehita DDR, ka taea e koe ma te Whakaora Taunoa. Kia mahara ka mukua e koe nga raraunga whirihoranga rehita katoa me kawemai ano koe, me whakauru ano ranei koe i enei raraunga. Ka tautuhia nga raraunga ki nga uara tautuhi taputapu.
Raraunga Hangaia
Pāwhiritia OK hei whakaputa i te whirihoranga. I runga i to whakaurunga ki nga ripa Whanui, Wā Mahara me te Whakakotahitanga Mahara, ka tatauhia e te Configurator MDDR nga uara mo nga rehita whirihoranga DDR katoa me te kaweake i enei uara ki to kaupapa firmware me te whaihanga. files. Ko te kaweake file ka whakaatuhia te wetereo ki te Whakaahua 2-6.

Firmware

Ka hangaia e koe te SmartDesign, ko nga mea e whai ake nei files ka hangaia i roto i te /firmware/ drivers_config/sys_config whaiaronga. Ko enei files e hiahiatia ana mo te matua rorohiko CMSIS ki te whakahiato tika me te whakauru i nga korero mo to hoahoa o naianei tae atu ki nga raraunga whirihoranga peripheral me nga korero whirihoranga karaka mo te MSS. Kaua e whakatika enei files ā-ringa i te mea ka hangaia ano i nga wa katoa ka hangaia ano to hoahoa pakiaka.

• sys_config.c
• sys_config.h
•  sys_config_mddr_define.h – Raraunga whirihoranga MDDR.
• Sys_config_fddr_define.h – Raraunga whirihoranga FDDR.
•  sys_config_mss_clocks.h – whirihoranga karaka MSS

whaihanga
Ka hangaia e koe te SmartDesign e hono ana ki to MSS, ko te whaihanga e whai ake nei files ka hangaia i roto i te / whaiaronga whaihanga:

•  whakamātautau.bfm – BFM taumata-runga file ka "whakamahia" tuatahi i te wa o te whaihanga e whakamahi ana i te tukatuka SmartFusion2 MSS 'Cortex-M3. Ka mahia te peripheral_init.bfm me te user.bfm, i roto i taua raupapa.
•  peripheral_init.bfm – Kei roto te tukanga BFM e whai ana i te mahi CMSIS::SystemInit() i runga i te Cortex-M3 i mua i to urunga ki te tikanga matua(). Ka kape i nga raraunga whirihoranga mo nga taputapu katoa e whakamahia ana i roto i te hoahoa ki nga rehita whirihoranga peripheral tika, ka tatari kia rite nga peripheral katoa i mua i te kii ka taea e te kaiwhakamahi te whakamahi i enei taputapu.
• MDDR_init.bfm – Kei roto nga whakahau tuhi BFM e whakataurite ana i nga tuhi o nga raraunga rehita whirihoranga MSS DDR i whakauruhia e koe (ma te whakamahi i te korero Whakatika Rehita i runga ake nei) ki nga rehita Kaiwhakahaere DDR.
• user.bfm – I whakaritea mo nga whakahau a te kaiwhakamahi. Ka taea e koe te whakataurite i te ara raraunga ma te taapiri i a koe ake whakahau BFM i tenei file. Nga whakahau i roto i tenei file ka "whakamahia" i muri i te otinga o te peripheral_init.bfm.

Te whakamahi i te files runga ake, te ara whirihoranga kua whakatairite aunoa. Me whakatika noa te kaiwhakamahi.bfm file ki te whakatairite i te ara raraunga. Kaua e whakatika i te test.bfm, peripheral_init.bfm, MDDR_init.bfm ranei files rite enei files ka hangaia ano i nga wa katoa ka hangaia ano to hoahoa pakiaka.

Ara Whirihoranga MSS DDR
E hiahia ana te otinga Whakawhanaketanga Awhiowhio, hei taapiri atu ki te whakarite i nga uara rehita whirihoranga MSS DDR, ka whirihora e koe te ara raraunga whirihoranga APB i roto i te MSS (FIC_2). Ko te mahinga SystemInit() ka tuhi i nga raraunga ki nga rehita whirihoranga MDDR ma te atanga FIC_2 APB.
Tuhipoka: Mena kei te whakamahi koe i te Kaihanga Pūnaha kua tautuhia te ara whirihoranga me te hono aunoa.

Hei whirihora i te atanga FIC_2:

1. Whakatuwheratia te korero whirihora FIC_2 (Whakaahua 2-7) mai i te whirihora MSS.
2. Tīpakohia te Arawhiti peripheral mā te kōwhiringa Cortex-M3.
3. Kia mohio kei te tirotirohia te MSS DDR, me nga poraka Fabric DDR/SERDES mena kei te whakamahi koe.
4.  Pāwhiritia OK hei tiaki i o tautuhinga. Ma tenei ka whakaatu i nga tauranga whirihoranga FIC_2 (Karaka, Tautuhi, me nga atanga pahi APB), penei i te Whakaahua 2-8.
5.  Hangaia te MSS. Ko nga tauranga FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK me FIC_2_APB_M_RESET_N) kua kitea inaianei ki te atanga MSS ka taea te hono atu ki te CoreConfigP me CoreResetP i runga i te whakatakotoranga otinga mo te Whakatairanga Whakawhiti.

Mo nga taipitopito katoa mo te whirihora me te hono i nga uho CoreConfigP me CoreResetP, tirohia te Aratohu Kaiwhakamahi Arataki Arataki.

Whakaahuatanga Tauranga

Atanga DDR PHY
Ripanga 3-1 • Atanga DDR PHY

Ingoa Tauranga	Te aronga	Whakaahuatanga
MDDR_CAS_N	KI WAHO	DRAM CASN
MDDR_CKE	KI WAHO	DRAM CKE
MDDR_CLK	KI WAHO	Karaka, taha P
MDDR_CLK_N	KI WAHO	Karaka, taha N
MDDR_CS_N	KI WAHO	DRAM CSN
MDDR_ODT	KI WAHO	DRAM ODT
MDDR_RAS_N	KI WAHO	DRAM RASN
MDDR_RESET_N	KI WAHO	Tautuhi DRAM mo DDR3. Waiho tenei tohu mo nga Atanga LPDDR me DDR2. Tohua kaore i whakamahia mo nga Atanga LPDDR me DDR2.
MDDR_WE_N	KI WAHO	DRAM WEN
MDDR_ADDR[15:0]	KI WAHO	Moka Wāhitau Dram
MDDR_BA[2:0]	KI WAHO	Wāhitau Peke Dram
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	ROTO	Maki Raraunga Dram
MDDR_DQS ([3:0]/[1:0]/[0])	ROTO	Tāuru Raraunga Strobe Whakauru/Putanga – P Taha
MDDR_DQS_N ([3:0]/[1:0]/[0])	ROTO	Tāuru Raraunga Strobe Whakauru/Putanga - N Taha
MDDR_DQ ([31:0]/[15:0]/[7:0])	ROTO	DRAM Raraunga Whakauru/Putanga
MDDR_DQS_TMATCH_0_IN	IN	FIFO i te tohu
MDDR_DQS_TMATCH_0_OUT	KI WAHO	FIFO puta tohu
MDDR_DQS_TMATCH_1_IN	IN	FIFO i te tohu (32-bit anake)
MDDR_DQS_TMATCH_1_OUT	KI WAHO	Tohu FIFO puta (32-bit anake)
MDDR_DM_RDQS_ECC	ROTO	Dram ECC Raraunga Raraunga
MDDR_DQS_ECC	ROTO	Dram ECC Raraunga Strobe Whakauru/Putanga - P Taha
MDDR_DQS_ECC_N	ROTO	Dram ECC Raraunga Strobe Whakauru/Putanga - N Taha
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	ROTO	DRAM ECC Raraunga Whakauru/Putanga
MDDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO hei tohu
MDDR_DQS_TMATCH_ECC_OUT	KI WAHO	ECC FIFO tohu waho (32-bit anake)

Tuhipoka: Ka huri nga whanui tauranga mo etahi tauranga i runga i te kowhiringa o te whanui PHY. Ko te tohu “[a:0]/ [b:0]/[c:0]” ka whakamahia hei tohu i aua tauranga, i reira ko “[a:0]” e tohu ana ki te whanui tauranga ina tohua te whanui PHY 32-bit. , “[b:0]” e hāngai ana ki te moka-16 te whanui PHY, me te “[c:0]” ki te moka-8 PHY whanui.

Atanga Pahi Matua AXI
Ripanga 3-2 • Atanga Pahi Matua AXI

Ingoa Tauranga	Te aronga	Whakaahuatanga
DDR_AXI_S_AWREADY	KI WAHO	Tuhia te wahitau kua rite
DDR_AXI_S_WREADY	KI WAHO	Tuhia te wahitau kua rite
DDR_AXI_S_BID[3:0]	KI WAHO	ID Whakautu
DDR_AXI_S_BRESP[1:0]	KI WAHO	Tuhia te whakautu
DDR_AXI_S_BVALID	KI WAHO	Tuhia he whakautu tika
DDR_AXI_S_ARREADY	KI WAHO	Kua rite te wahitau panui
DDR_AXI_S_RID[3:0]	KI WAHO	Panui ID Tag
DDR_AXI_S_RRESP[1:0]	KI WAHO	Panui Whakautu
DDR_AXI_S_RDATA[63:0]	KI WAHO	Panui raraunga
DDR_AXI_S_RLAST	KI WAHO	Panui Whakamutunga Ka tohu tenei tohu i te whakawhitinga whakamutunga i roto i te pakaru panui
DDR_AXI_S_RVALID	KI WAHO	Pānuihia te wāhitau whaimana
DDR_AXI_S_AWID[3:0]	IN	Tuhia ID Wāhitau
DDR_AXI_S_AWADDR[31:0]	IN	Tuhia te wahitau
DDR_AXI_S_AWLEN[3:0]	IN	Te roa pakaru
DDR_AXI_S_AWSIZE[1:0]	IN	Rahi pakaru
DDR_AXI_S_AWBURST[1:0]	IN	Momo pakaru
DDR_AXI_S_AWLOCK[1:0]	IN	Momo maukati Ko tenei tohu he korero taapiri mo nga ahuatanga ngota o te whakawhitinga
DDR_AXI_S_AWVALID	IN	Tuhia te wahitau whaimana
DDR_AXI_S_WID[3:0]	IN	Tuhia ID Raraunga tag
DDR_AXI_S_WDATA[63:0]	IN	Tuhia nga raraunga
DDR_AXI_S_WSTRB[7:0]	IN	Tuhia nga pupuhi
DDR_AXI_S_WLAST	IN	Tuhia whakamutunga
DDR_AXI_S_WVALID	IN	Tuhia tika
DDR_AXI_S_BREADY	IN	Tuhia kua rite
DDR_AXI_S_ARID[3:0]	IN	Pānuihia te ID Wāhitau
DDR_AXI_S_ARADDR[31:0]	IN	Pānuihia te wāhi noho
DDR_AXI_S_ARLEN[3:0]	IN	Te roa pakaru
DDR_AXI_S_ARSIZE[1:0]	IN	Rahi pakaru
DDR_AXI_S_ARBURST[1:0]	IN	Momo pakaru
DDR_AXI_S_ARLOCK[1:0]	IN	Momo Maukati
DDR_AXI_S_ARVALID	IN	Pānuihia te wāhitau whaimana
DDR_AXI_S_RREADY	IN	Kua rite te wahitau panui

Ripanga 3-2 • Atanga Pahi Matua AXI (kei te haere tonu)

Ingoa Tauranga	Te aronga	Whakaahuatanga
DDR_AXI_S_CORE_RESET_N	IN	MDDR Tautuhi Ao
DDR_AXI_S_RMW	IN	Ka tohu mehemea he tika nga paita katoa o te ara 64 bit mo nga pao katoa o te whakawhiti AXI. 0: E tohu ana ko nga paita katoa i roto i nga pao katoa he whaimana i roto i te pakaru, a me taunoa te kaiwhakahaere ki te tuhi whakahau 1: E tohu ana he muhu etahi paita, me taunoa te kaiwhakahaere ki nga whakahau RMW Ka whakarōpūhia tenei hei tohu AXI tuhi korero mo te hongere taha taha ka whai mana me te tohu AWVALID. Ka whakamahia anake ina whakahohea te ECC.

Atanga Pahi Matua AHB0
Ripanga 3-3 • Atanga Pahihiko AHB0 Kaiwhakaako papanga

Ingoa Tauranga	Te aronga	Whakaahuatanga
DDR_AHB0_SHREADYOUT	KI WAHO	Kua reri te taurekareka AHBL – I te wa teitei mo te tuhi e tohu ana kua reri te MDDR ki te whakaae ki nga raraunga me te teitei mo te panui ka tohu he tika nga raraunga
DDR_AHB0_SHRESP	KI WAHO	Te mana whakautu AHBL - Ina peia teitei i te mutunga o te tauwhitinga ka tohu kua oti te whakawhitinga me nga hapa. Ina peia iti i te mutunga o te tauwhitinga ka tohu kua oti pai te tauwhitinga.
DDR_AHB0_SHRDATA[31:0]	KI WAHO	AHBL panui raraunga - Panui raraunga mai i te pononga MDDR ki te rangatira papanga
DDR_AHB0_SHSEL	IN	Kowhiria te pononga AHBL - I te wa e kii ana, ko te MDDR te taurekareka AHBL kua tohua i runga i te papanga AHB pahi
DDR_AHB0_SHADDR[31:0]	IN	Wāhitau AHBL – wāhitau paita i runga i te atanga AHBL
DDR_AHB0_SHBURST[2:0]	IN	AHBL Putanga Roa
DDR_AHB0_SHSIZE[1:0]	IN	Rahi whakawhiti AHBL – He tohu te rahi o te whakawhitinga o naianei (8/16/32 paita noa nga whakawhitinga)
DDR_AHB0_SHTRANS[1:0]	IN	Momo whakawhiti AHBL - E whakaatu ana i te momo whakawhiti o te tauwhitinga o naianei
DDR_AHB0_SHMASTLOCK	IN	Maukati AHBL - I te wa e kii ana ko te whakawhitinga o naianei he waahanga o te tauwhitinga raka
DDR_AHB0_SHWRITE	IN	Tuhituhi AHBL – Ina tohu teitei ko te tauwhitinga o naianei he tuhi. Ina he iti te tohu he panui te tauwhitinga o naianei
DDR_AHB0_S_HREADY	IN	Kua rite te AHBL - Ina teitei, ka tohu kua reri te MDDR ki te whakaae ki tetahi tauwhitinga hou
DDR_AHB0_S_HWDATA[31:0]	IN	AHBL tuhi raraunga - Tuhia nga raraunga mai i te rangatira papanga ki te MDDR

Atanga Pahi Matua AHB1
Ripanga 3-4 • Atanga Pahihiko AHB1 Kaiwhakaako papanga

Ingoa Tauranga	Te aronga	Whakaahuatanga
DDR_AHB1_SHREADYOUT	KI WAHO	Kua reri te taurekareka AHBL – I te wa teitei mo te tuhi e tohu ana kua reri te MDDR ki te whakaae ki nga raraunga me te teitei mo te panui ka tohu he tika nga raraunga
DDR_AHB1_SHRESP	KI WAHO	Te mana whakautu AHBL - Ina peia teitei i te mutunga o te tauwhitinga ka tohu kua oti te whakawhitinga me nga hapa. Ina peia iti i te mutunga o te tauwhitinga ka tohu kua oti pai te tauwhitinga.
DDR_AHB1_SHRDATA[31:0]	KI WAHO	AHBL panui raraunga - Panui raraunga mai i te pononga MDDR ki te rangatira papanga
DDR_AHB1_SHSEL	IN	Kowhiria te pononga AHBL - I te wa e kii ana, ko te MDDR te taurekareka AHBL kua tohua i runga i te papanga AHB pahi
DDR_AHB1_SHADDR[31:0]	IN	Wāhitau AHBL – wāhitau paita i runga i te atanga AHBL
DDR_AHB1_SHBURST[2:0]	IN	AHBL Putanga Roa
DDR_AHB1_SHSIZE[1:0]	IN	Rahi whakawhiti AHBL – He tohu te rahi o te whakawhitinga o naianei (8/16/32 paita noa nga whakawhitinga)
DDR_AHB1_SHTRANS[1:0]	IN	Momo whakawhiti AHBL - E whakaatu ana i te momo whakawhiti o te tauwhitinga o naianei
DDR_AHB1_SHMASTLOCK	IN	Maukati AHBL - I te wa e kii ana ko te whakawhitinga o naianei he waahanga o te tauwhitinga raka
DDR_AHB1_SHWRITE	IN	Tuhituhi AHBL – Ina tohu teitei ko te tauwhitinga o naianei he tuhi. Ina he iti te tohu he panui te tauwhitinga o naianei.
DDR_AHB1_SHREADY	IN	Kua rite te AHBL - Ina teitei, ka tohu kua reri te MDDR ki te whakaae ki tetahi tauwhitinga hou
DDR_AHB1_SHWDATA[31:0]	IN	AHBL tuhi raraunga - Tuhia nga raraunga mai i te rangatira papanga ki te MDDR

Aratau Kaiwhakahaere Mahara ngawari AXI Bus Atanga
Ripanga 3-5 • Aratau Kaiwhakahaere Mahara ngawari AXI Bus Atanga

Ingoa Tauranga	Te aronga	Whakaahuatanga
SMC_AXI_M_WLAST	KI WAHO	Tuhia whakamutunga
SMC_AXI_M_WVALID	KI WAHO	Tuhia tika
SMC_AXI_M_AWLEN[3:0]	KI WAHO	Te roa pakaru
SMC_AXI_M_AWBURST[1:0]	KI WAHO	Momo pakaru
SMC_AXI_M_BREADY	KI WAHO	Kua rite te whakautu
SMC_AXI_M_AWVALID	KI WAHO	Tuhia te Wāhitau Whaimana
SMC_AXI_M_AWID[3:0]	KI WAHO	Tuhia ID Wāhitau
SMC_AXI_M_WDATA[63:0]	KI WAHO	Tuhia Raraunga
SMC_AXI_M_ARVALID	KI WAHO	Pānuihia te wāhitau whaimana
SMC_AXI_M_WID[3:0]	KI WAHO	Tuhia ID Raraunga tag
SMC_AXI_M_WSTRB[7:0]	KI WAHO	Tuhia nga pupuhi
SMC_AXI_M_ARID[3:0]	KI WAHO	Pānuihia te ID Wāhitau
SMC_AXI_M_ARADDR[31:0]	KI WAHO	Pānuihia te wāhi noho
SMC_AXI_M_ARLEN[3:0]	KI WAHO	Te roa pakaru
SMC_AXI_M_ARSIZE[1:0]	KI WAHO	Rahi pakaru
SMC_AXI_M_ARBURST[1:0]	KI WAHO	Momo pakaru
SMC_AXI_M_AWADDR[31:0]	KI WAHO	Tuhia Wāhitau
SMC_AXI_M_RREADY	KI WAHO	Kua rite te wahitau panui
SMC_AXI_M_AWSIZE[1:0]	KI WAHO	Rahi pakaru
SMC_AXI_M_AWLOCK[1:0]	KI WAHO	Momo maukati Ko tenei tohu he korero taapiri mo nga ahuatanga ngota o te whakawhitinga
SMC_AXI_M_ARLOCK[1:0]	KI WAHO	Momo Maukati
SMC_AXI_M_BID[3:0]	IN	ID Whakautu
SMC_AXI_M_RID[3:0]	IN	Panui ID Tag
SMC_AXI_M_RESP[1:0]	IN	Panui Whakautu
SMC_AXI_M_BRESP[1:0]	IN	Tuhia te whakautu
SMC_AXI_M_AWREADY	IN	Tuhia te wahitau kua rite
SMC_AXI_M_RDATA[63:0]	IN	Panui Raraunga
SMC_AXI_M_WREADY	IN	Tuhia kua rite
SMC_AXI_M_BVALID	IN	Tuhia he whakautu tika
SMC_AXI_M_ARREADY	IN	Kua rite te wahitau panui
SMC_AXI_M_RLAST	IN	Panui Whakamutunga Ka tohu tenei tohu i te whakawhitinga whakamutunga i roto i te pakaru panui
SMC_AXI_M_RVALID	IN	Panui Whaimana

Aratau Kaiwhakahaere Mahara Mahara AHB0 Atanga Pahi
Ripanga 3-6 • Aratau Kaiwhakahaere Mahara Mahara AHB0 Atanga pahi

Ingoa Tauranga	Te aronga	Whakaahuatanga
SMC_AHB_M_HBURST[1:0]	KI WAHO	AHBL Putanga Roa
SMC_AHB_M_HTRANS[1:0]	KI WAHO	Momo whakawhiti AHBL - E whakaatu ana i te momo whakawhiti o te tauwhitinga o naianei.
SMC_AHB_M_HMASTLOCK	KI WAHO	Maukati AHBL - I te wa e kii ana ko te whakawhitinga o naianei he waahanga o te tauwhitinga raka
SMC_AHB_M_HWRITE	KI WAHO	Tuhituhi AHBL — Ina tohu teitei ko te tauwhitinga o naianei he tuhi. Ina he iti te tohu he panui te tauwhitinga o naianei
SMC_AHB_M_HSIZE[1:0]	KI WAHO	Rahi whakawhiti AHBL – He tohu te rahi o te whakawhitinga o naianei (8/16/32 paita noa nga whakawhitinga)
SMC_AHB_M_HWDATA[31:0]	KI WAHO	AHBL tuhi raraunga - Tuhia nga raraunga mai i te rangatira MSS ki te papanga Soft Memory Controller
SMC_AHB_M_HADDR[31:0]	KI WAHO	Wāhitau AHBL – wāhitau paita i runga i te atanga AHBL
SMC_AHB_M_HRESP	IN	Te mana whakautu AHBL - Ina peia teitei i te mutunga o te tauwhitinga ka tohu kua oti te mahi me nga hapa. Ina peia iti i te mutunga o te tauwhitinga ka tohu kua oti pai te tauwhitinga
SMC_AHB_M_HRDATA[31:0]	IN	AHBL panui raraunga - Panuihia nga raraunga mai i te papanga Soft Memory Controller ki te rangatira MSS
SMC_AHB_M_HREADY	IN	Kua reri te AHBL – Ko te teitei e tohu ana kua reri te pahi AHBL ki te whakaae ki tetahi tauwhitinga hou

Tautoko Hua

Ko te Roopu Hua Microsemi SoC e tautoko ana i ana hua me nga momo ratonga tautoko, tae atu ki te Ratonga Kaihoko, Pokapu Tautoko Hangarau Kiritaki, a webpae, mēra hiko, me nga tari hoko o te ao. Kei roto i tenei taapiri nga korero mo te whakapiri atu ki te Roopu Hua Microsemi SoC me te whakamahi i enei ratonga tautoko.
Ratonga Kiritaki
Whakapa atu ki te Ratonga Kaihoko mo te tautoko hua kore-hangarau, penei i te utu hua, te whakahou i nga hua, nga korero whakahou, te mana ota, me te whakamanatanga.
Mai i Amerika Te Tai Tokerau, waea atu ki 800.262.1060
Mai i te ao katoa, waea atu ki 650.318.4460
Waeatuhi, mai i nga waahi katoa o te ao, 650.318.8044
Pokapū Tautoko Hangarau Kiritaki
Ko te Roopu Microsemi SoC Products e mahi ana i tana Pokapū Tautoko Hangarau Kaihoko me nga miihini tino mohio ka taea te awhina ki te whakautu i o patai taputapu, rorohiko, hoahoa hoki mo nga Hua Microsemi SoC. He nui te wa e whakapaua ana e te Pokapū Tautoko Hangarau Kiritaki ki te hanga tuhipoka tono, whakautu ki nga patai huringa hoahoa noa, tuhinga mo nga take e mohiotia ana, me nga momo FAQ. No reira, i mua i to whakapiri mai ki a matou, tena koa toro mai ki a maatau rauemi ipurangi. Tena pea kua whakautua e matou o patai.
Tautoko Hangarau
Mo te Tautoko Hua Microsemi SoC, toro http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.
Webpae
Ka taea e koe te tirotiro i nga momo korero hangarau me te kore-hangarau i runga i te wharangi kaainga Microsemi SoC Products Group, i www.microsemi.com/soc.
Te whakapā atu ki te Pokapū Tautoko Hangarau Kiritaki
Ko nga miihini tino mohio nga kaimahi i te Whare Tautoko Hangarau. Ka taea te whakapā atu ki te Pokapū Tautoko Hangarau ma te imeera, ma te Microsemi SoC Products Group ranei webpae.
Īmēra
Ka taea e koe te korero i o patai hangarau ki to maatau wahitau imeera me te whakahoki whakautu ma te imeera, waea whakaahua, waea ranei. Ano, mena he raru to hoahoa, ka taea e koe te imeera i to hoahoa files ki te whiwhi awhina. Ka aroturuki matou i te kaute imeera puta noa i te ra. Ina tukuna mai to tono ki a matou, me whakauru mai to ingoa katoa, ingoa kamupene, me o korero whakapā mo te tukatuka pai o to tono.
Ko te wahitau imeera tautoko hangarau soc_tech@microsemi.com.
Aku Take
Ka taea e nga kaihoko a Microsemi SoC Products Group te tuku me te whai i nga keehi hangarau ma te ipurangi ma te haere ki aku Take.
Kei waho o te US
Ko nga kaihoko e hiahia ana ki te awhina i waho o nga rohe wa US ka taea te whakapā atu ki te tautoko hangarau ma te imeera (soc_tech@microsemi.com) whakapā atu ranei ki tetahi tari hoko rohe.
Tirohia mo matou mo nga rarangi tari hoko me nga hoapaki umanga.
Ka kitea nga raarangi tari hokohoko i www.microsemi.com/soc/company/contact/default.aspx.
Tautoko Hangarau ITAR
Mo te tautoko hangarau mo nga RH me te RT FPGA e whakahaerea ana e te International Traffic in Arms Regulations (ITAR), whakapā mai ma soc_tech_itar@microsemi.com. Hei tauira, i roto i aku Take, tohua Ae i te rarangi taka-iho ITAR. Mo te rarangi katoa o nga Microsemi FPGA kua whakaritea e ITAR, tirohia te ITAR web wharangi.

Mo Microsemi
Ko te Microsemi Corporation (Nasdaq: MSCC) e tuku ana i tetahi kopaki matawhānui o te semiconductor me nga otinga punaha mo te whakawhitiwhiti korero, te parepare me te haumarutanga, aerospace me nga maakete ahumahi. Ko nga hua kei roto i nga mahi teitei me te whakamaarama iraruke-whakapakeke i nga iahiko whakauru-tohu whakauru, nga FPGA, nga SoC me nga ASIC; hua whakahaere mana; te wa me nga taputapu tukutahi me nga otinga wa tika, te whakarite i te paerewa o te ao mo te waa; nga taputapu tukatuka reo; Nga rongoā RF; nga waahanga motuhake; Nga rongoatanga Rokiroki me te Whakawhitiwhiti hinonga, nga hangarau haumaru me te anti-t tauineineamper hua; Nga rongoā Ethernet; Ko nga IC me nga waahi-waenganui-a-hiko; me nga kaha hoahoa ritenga me nga ratonga. Ko Microsemi te tari matua i Aliso Viejo, Calif. a he tata ki te 4,800 nga kaimahi puta noa i te ao. Ako atu i www.microsemi.com.
Karekau a Microsemi he whakamana, he tohu, he taurangi ranei e pa ana ki nga korero kei konei, ki te tika ranei o ana hua me ana ratonga mo tetahi kaupapa motuhake, kaore ano hoki a Microsemi e kii he nama ahakoa ka puta mai i te tono me te whakamahi i tetahi hua, iahiko ranei. Ko nga hua e hokona ana i raro nei me etahi atu hua e hokona ana e Microsemi he iti noa te whakamatautau me te kore e whakamahia i te taha o nga taputapu miihana, tono ranei. Ko nga whakaritenga mahi e whakaponohia ana he pono engari kaore i te manatokohia, a me whakahaere e te Kaihoko nga mahi katoa me etahi atu whakamatautau o nga hua, ko ia anake me te whakauru, ka whakauruhia ranei ki roto i nga hua mutunga. Kaua te Kaihoko e whakawhirinaki ki nga raraunga me nga whakaritenga mahi me nga tawhā e whakaratohia ana e Microsemi. Ko te kawenga a te Kaihoko ki te whakatau takitahi i te pai o nga hua me te whakamatau me te manatoko i aua hua. Ko nga korero e whakaratohia ana e Microsemi i raro nei ka whakaratohia "penei, kei hea" me nga hapa katoa, a ko te katoa o te raruraru e pa ana ki aua korero kei te Kaihoko katoa. Karekau a Microsemi e tuku, maataki, maataki ranei, ki tetahi taha tetahi mana patent, raihana, etahi atu mana IP ranei, ahakoa mo aua korero ake, mo tetahi mea ranei e whakaahuatia ana e aua korero. Ko nga korero e whakaratohia ana i roto i tenei tuhinga he mana ki a Microsemi, a ko Microsemi te mana ki te whakarereke i nga korero i roto i tenei tuhinga, ki nga hua me nga ratonga i nga wa katoa kaore he panui.

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5-02-00377-5/11.16

Tuhinga / Rauemi

Microsemi SmartFusion2 MSS DDR Whirihoranga Kaiwhakahaere [pdf] Aratohu Kaiwhakamahi SmartFusion2 MSS DDR Whirihoranga Kaiwhakahaere, SmartFusion2 MSS, Whirihoranga Kaiwhakahaere DDR, Whirihoranga Kaiwhakahaere

Tohutoro

• Pukapuka Kaiwhakamahi