Ihirangi huna
1 intel F-Tile CPRI PHY FPGA IP Hoahoa Example
2 Aratohu Timata Tere
2.1 Nga Whakaritenga Pumau me nga Pūmanawa
2.2 Te whakaputa i te Hoahoa
2.3 Hanganga Whaiaronga
2.4 Whakataurite i te Hoahoa Exampte Testbench
2.5 Te whakahiato i te Kaupapa Whakaemi-anake
2.6 Te whakahiato me te whirihora i te Hoahoa Example i roto i nga taputapu
2.7 Whakamātautau i te Hoahoa Pūmārō Example
3 Hoahoa Example Whakaahuatanga
3.1 Ngā āhuatanga
3.2 Hoahoa whaihanga Example
3.3 Hoahoa Pūmārō Example
3.4 Tohu Atanga
3.5 Hoahoa Example Rehita
4 F-Tile CPRI PHY Intel FPGA IP Hoahoa Example Archives Aratohu Kaiwhakamahi
5 Tuhinga o mua mo te F-Tile CPRI PHY Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi
6 Tuhinga / Rauemi
6.1 Tohutoro
7 Whakairinga Paanga

tohu intel

intel F-Tile CPRI PHY FPGA IP Hoahoa Example

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte hua

Aratohu Timata Tere

Ko te F-Tile CPRI PHY Intel® FPGA IP matua e whakarato ana i te papa whakamatautau whaihanga me te hoahoa taputapu exampe tautoko ana i te whakahiato me te whakamatautau taputapu. Ina whakaputa koe i te hoahoa exampte, te ētita tawhā hanga aunoa i te files e tika ana ki te whaihanga, whakahiato, me te whakamatautau i te hoahoa i roto i te taputapu.
Ka whakarato hoki a Intel i te whakahiato-anakeampte kaupapa ka taea e koe te whakamahi ki te whakatau tere i te rohe matua IP me te wa.
Ko te F-Tile CPRI PHY Intel FPGA IP matua e whakarato ana i te kaha ki te whakaputa hoahoa exampmo nga huinga tautoko katoa o te maha o nga hongere CPRI me nga reiti moka raina CPRI. Ko te papa whakamatautau me te hoahoa exampKa tautokohia nga huinga tawhā maha o te F-Tile CPRI PHY Intel FPGA IP matua.

Whakaatu 1. Nga Waahi Whanaketanga mo te Hoahoa Example

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 1

Nga korero e pa ana

  • F-Tile CPRI PHY Intel FPGA IP Aratohu Kaiwhakamahi
    • Mo nga korero taipitopito mo te F-tile CPRI PHY IP.
  • F-Tile CPRI PHY Intel FPGA IP Release Notes
    • Ko te rarangi IP Release Notes nga huringa IP i roto i tetahi tukunga.
Nga Whakaritenga Pumau me nga Pūmanawa

Hei whakamatautau i te exampte hoahoa, whakamahia nga taputapu me nga rorohiko e whai ake nei:

  • Pūmanawa Intel Quartus® Prime Pro Edition
  • Papatohu Pūnaha
  • Simulators Tautokohia:
    • Synopsys* VCS*
    • Synopsys VCS MX
    • Siemens* EDA ModelSim* SE or Questa*— Questa-Intel FPGA Edition
Te whakaputa i te Hoahoa

Whakaatu 2. Tikanga

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 2Whakaahua 3. Exampte Ripa Hoahoa i roto i te Kaiwhakatika Tawhā IP

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 3

Hei waihanga kaupapa Intel Quartus Prime Pro Edition:

  1. I roto i te Intel Quartus Prime Pro Edition, pawhiria File ➤ Ruānuku Kaupapa Hou hei hanga kaupapa hou a Quartus Prime, ranei File ➤ Kaupapa Tuwhera hei whakatuwhera i tetahi kaupapa Intel Quartus Prime. Ka akiaki koe e te ruānuku ki te tautuhi i tetahi taputapu.
  2. Tauwhāitihia te whanau taputapu Agilex (I-raupapa) ka kowhiri i tetahi taputapu e tutuki ana i enei whakaritenga katoa:
    • Ko te taera whakawhiti he F-tile
    • Ko te tohu tere whakawhiti he -1, -2 ranei
    • Ko te kōeke tere matua -1, -2, -3 ranei
  3. Pāwhiritia te Mutu.

A pee i enei mahi ki te whakaputa i te F-Tile CPRI PHY Intel FPGA IP hoahoa taputapu example me te papa whakamatautau:

  1. I roto i te Putumōhio IP, kimihia ka tohua te F-Tile CPRI PHY Intel FPGA IP. Ka puta te matapihi Rerekē IP Hou.
  2. Tauwhāitihia he ingoa taumata-runga mo to rereketanga IP ritenga. Ka tiakina e te ētita tawhā ngā tautuhinga rerekētanga IP i roto i te a file whakaingoatia .ip.
  3. Pāwhiritia OK. Ka puta te ētita tawhā.
  4. I te ripa IP, whakapūtāhia ngā tawhā mō tō rerekētanga matua IP.
  5. I runga i te Exampripa Hoahoa, i raro i Example Hoahoa Files, tīpakohia te kōwhiringa Simulation ki te whakaputa i te papamahi whakamatautau me te kaupapa whakahiato-anake. Tīpakohia te kōwhiringa Synthesis ki te whakaputa i te hoahoa taputapu example. Me kowhiria e koe tetahi o nga whiringa Whakaakoranga me te Synthesis hei whakaputa i te hoahoa o muaample.
  6. I runga i te Exampte ripa Hoahoa, i raro i te Hōputu HDL Hangaia, tohua te Verilog HDL me te VHDL ranei. Mena ka kowhiria e koe te VHDL, me whakatairite koe i te papae whakamatautau me te simulator reo whakauru. Ko te taputapu kei te whakamatautauria i te ex_ Ko te whaiaronga he tauira VHDL, engari ko te papa whakamatautau matua file he Pūnaha Verilog file.
  7. Pāwhiritia te Hanga Exampte pātene Hoahoa. Ko te Tohu Exampka puta te matapihi Design Directory.
  8. Mena kei te hiahia koe ki te whakarereke i te hoahoa exampte ara whaiaronga, ingoa ranei mai i nga taunoa kua whakaatuhia (cpriphy_ftile_0_example_design), tirotiro ki te ara hou ka pato i te hoahoa hou exampte ingoa whaiaronga (ample_dir>).
Hanganga Whaiaronga

Ko te F-Tile CPRI PHY Intel FPGA IP hoahoa matua example file kei roto i nga whaiaronga nga mea hanga e whai ake nei files mo te hoahoa example.

Whakaatu 4. Hanganga Whaiaronga o te Ex Generated Example Hoahoa

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 4

Ripanga 1. Taumatau File Whakaahuatanga

File Nga Ingoa Whakaahuatanga
Te Paepae Whakamatau Matua me te Whakaaturanga Files
<design_example_dir>/ example_testbench/basic_avl_tb_top.sv Te pae whakamatautau taumata-runga file. Ka tukuna e te papa whakamatautau te takai DUT me te whakahaere i nga mahi a Verilog HDL hei whakaputa me te whakaae i nga paanui.
<design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv Ko te takai DUT e whakaputa ana i te DUT me etahi atu waahanga whakamatautau.
Nga Tuhi Whakamatau(1)
<design_example_dir>/ example_testbench/run_vsim.do Ko te Siemens EDA ModelSim SE, Questa, Questa-Intel FPGA Edition ranei hei whakahaere i te papa whakamatautau.
<design_example_dir>/ example_testbench/run_vcs.sh Ko te tuhinga Synopsys VCS hei whakahaere i te papa whakamatautau.
<design_example_dir>/ example_testbench/run_vcsmx.sh Ko te Synopsys VCS MX hōtuhi (kua honoa te Verilog HDL me te SystemVerilog me te VHDL) hei whakahaere i te papa whakamatautau.

Kaua e aro ki tetahi atu tuhinga simulator i roto i teample_dir>/example_testbench/ kōpaki.

Ripanga 2. Hoahoa Pūmārō Example File Whakaahuatanga

File Nga Ingoa Whakaahuatanga
<design_example_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_hw.qpf Kaupapa Intel Quartus Prime file.
<design_example_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_hw.qsf Tautuhinga kaupapa Intel Quartus Prime file.
<design_example_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_hw.sdc Nga herenga Hoahoa Synopsys files. Ka taea e koe te kape me te whakarereke i enei filemo to ake hoahoa Intel Agilex™.
<design_example_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_hw.v Hoahoa Verilog HDL taumata-rungaample file.
<design_example_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_wrapper.sv Ko te takai DUT e whakaputa ana i te DUT me etahi atu waahanga whakamatautau.
<design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl Matua file mo te uru atu ki te Papatohu Pūnaha.
Whakataurite i te Hoahoa Exampte Testbench

Whakaatu 5. Tikanga

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 5

A pee i enei taahiraa hei whakatauira i te papa whakamatautau:

  1. I te whakahau whakahau, huri ki te whaiaronga whaihanga testbenchample_dir>/example_testbench. cd /example_testbench
  2. Whakahaerehia te quartus_tlg i runga i te kaupapa i hangaia file: quartus_tlg cpriphy_ftile_hw
  3. Whakahaere ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
  4. Whakahaerehia te tuhinga whaihanga mo te simulator tautoko e pai ana koe. Ka whakahiato, ka whakahaeretia e te tuhinga te papa whakamatautau i roto i te simulator. Tirohia te ripanga.
  5. Tātarihia ngā hua. I whiwhihia e te papa whakamatautau angitu e rima nga anga-itua, me te whakaatu i te "PASSED".

Ripanga 3. Nga Hipanga ki te Whakataurite i te Testbench i Synopsys VCS* Simulator

Simulator Tohutohu
VCS I roto i te raina whakahau, pato:
sh run_vcs.sh  
haere tonu…
Simulator Tohutohu
VCS MX I roto i te raina whakahau, pato:
sh run_vcsmx.sh  
ModelSim SE, Questa, Questa-Intel FPGA Edition ranei I roto i te raina whakahau, pato:
vsim -do run_vsim.do  
Ki te hiahia koe ki te whaihanga me te kore e kawe ake i te GUI, pato:
vsim -c -do run_vsim.do  

Ko nga s e whai ake neiampKo te putanga e whakaatu ana i te oma whakamatautau whaihanga angitu mo te 24.33024 Gbps me nga hongere CPRI e 4:

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 9 intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 10 intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 11

Te whakahiato i te Kaupapa Whakaemi-anake

Hei whakahiato i te whakahiato-anake exampte kaupapa, whai i enei mahi:

  1. Me whakarite hoahoa whakahiato exampkua oti te reanga.
  2. I roto i te rorohiko Intel Quartus Prime Pro Edition, whakatuwheratia te kaupapa Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
  3. I te tahua Tukatuka, pawhiria te Tīmata Whakahiato.
  4. Whai muri i te whakahiato angitu, ka watea mai nga purongo mo te wa me te whakamahi rawa i to wahanga Intel Quartus Prime Pro Edition.

Nga korero e pa ana
Nga Rerenga Hoahoa Poraka

Te whakahiato me te whirihora i te Hoahoa Example i roto i nga taputapu

Hei whakahiato i te hoahoa taputapu exampme te whirihora i runga i to taputapu Intel Agilex, whai i enei mahi:

  1. Whakaritea te hoahoa taputapu exampkua oti te reanga.
  2. I roto i te rorohiko Intel Quartus Prime Pro Edition, whakatuwheratia te kaupapa Intel Quartus Primeample_dir>/puru_whakamatautau_hoahoa/ cpriphy_ftile_hw.qpf.
  3. Whakatikahia te .qsf file ki te tautapa titi i runga i to taputapu.
  4. I te tahua Tukatuka, pawhiria te Tīmata Whakahiato.
  5. Whai muri i te whakahiato angitu, he .sof file e wātea ana i roto iample_dir>/puru_whakamatautau_hoahoa/putanga_files whaiaronga.

A pee i enei mahi ki te whakarite i te hoahoa taputapu exampi runga i te taputapu Intel Agilex:

  • Honoa Intel Agilex I-series Transceiver Signal Integrity Development Kit ki te rorohiko manaaki.
    Kia mahara: Ko te kete whanaketanga kua whakahoahoa me nga iarere karaka tika ma te taunoa. Kaore koe e hiahia ki te whakamahi i te tono Mana Karaka ki te tautuhi i nga iarere.
  • I runga i te tahua Utauta, pawhiria te Kaihōtaka.
  • I roto i te Kaihōtaka, pāwhiritia te Tatūnga Pūmārō.
  • Tīpakohia he taputapu hōtaka.
  • Me whakarite kua tautuhia te Aratau ki a JTAG.
  • Tīpakohia te taputapu Intel Agilex ka paato i te Tāpiri Pūrere. Ka whakaatuhia e te Kaihōtaka he hoahoa paraka o nga hononga i waenga i nga taputapu i runga i to papa.
  • I te rarangi me to .sof, tirohia te pouaka mo te .sof.
  • Takina te pouaka kei te rarangi Papatono/Whirihora.
  • Pāwhiritia Tīmata.

Nga korero e pa ana

  • Nga Rerenga Hoahoa Poraka
  • Papatonotanga Intel FPGA Pūrere
  • Te Tatari me te Patuiro Hoahoa me te Papatohu Pūnaha
Whakamātautau i te Hoahoa Pūmārō Example

I muri i to whakahiato i te F-Tile CPRI PHY Intel FPGA IP hoahoa matua exampme te whirihora i runga i to taputapu Intel Agilex, ka taea e koe te whakamahi i te Papatohu Pūnaha ki te whakarite i te matua IP me ona rehitatanga matua PHY IP.
Hei whakakā i te Pūnaha Papatohu me te whakamatautau i te hoahoa taputapu exampe, whai i enei kaupae:

  1. I muri i te hoahoa taputapu exampKua whirihorahia i runga i te taputapu Intel Agilex, i roto i te rorohiko Intel Quartus Prime Pro Edition, i runga i te tahua Utauta, pawhiria nga Utauta Patuiro Pūnaha ➤ Papatohu Pūnaha.
  2. I te pihanga Tcl Console, patohia te cd hwtest hei huri i te whaiaronga kiample_dir>/puru_whakamatautau_hoahoa/hwtest_sl.
  3. Patohia te puna main_script.tcl hei whakatuwhera hononga ki te JTAG rangatira ka timata te whakamatautau.

Hoahoa Example Whakaahuatanga

Ko te hoahoa exampe whakaatu ana i te mahinga taketake o te F-Tile CPRI PHY Intel FPGA IP matua. Ka taea e koe te whakaputa i te hoahoa mai i te Exampte ripa Hoahoa i roto i te F-Tile CPRI PHY Intel FPGA IP ētita tawhā.
Hei whakaputa i te hoahoa exampNa, me whakarite e koe nga uara tawhā mo te rereketanga matua IP e hiahia ana koe ki te whakaputa i to hua mutunga. Ka taea e koe te whiriwhiri ki te whakaputa i te hoahoa exampme te kore ranei te waahanga RS-FEC. Kei te waatea te waahanga RS-FEC me te 10.1376, 12.1651 me te 24.33024 Gbps CPRI reiti moka raina.
Ripanga 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix

Auau Moka Raina CPRI (Gbps) Tautoko RS-FEC Karaka Tohutoro (MHz) Tautoko Rorohiko Whakatau
1.2288 Kao 153.6 Ae
2.4576 Kao 153.6 Ae
3.072 Kao 153.6 Ae
4.9152 Kao 153.6 Ae
6.144 Kao 153.6 Ae
9.8304 Kao 153.6 Ae
10.1376 Me te Kore 184.32 Ae
12.1651 Me te Kore 184.32 Ae
24.33024 Me te Kore 184.32 Ae
Ngā āhuatanga
  • Hangaia te hoahoa exampme te waahanga RS-FEC
  • Ko nga kaha ki te tirotiro i nga paatete, tae atu ki te tatau mo nga haerenga a tawhio noa
Hoahoa whaihanga Example

Ko te F-Tile CPRI PHY Intel FPGA IP hoahoa exampKa hangaia e ia he papa whakamatautau me te whaihanga files e instantiates te F-Tile CPRI PHY Intel FPGA IP matua ina kowhiria e koe te whiringa Whakaaturanga.

Whakaahua 6. Hoahoa Poraka mo te 10.1316, 12.1651, me te 24.33024 Gbps (me te kore RS-FEC) Reiti Raina

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 6Whakaatu 7. Hoahoa Poraka mo te 1.228, 2.4576, 3.072, 4.9152, 6.144, me te 9.8304 Gbps Raina Raina

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 7

I roto i tenei hoahoa exampNa, ka whakaratohia e te papa whakamatautau whaihanga nga mahi taketake penei i te whakaoho me te tatari mo te raka, te tuku me te tango i nga putea.
Ko te oma whakamatautau angitu ka whakaatu i te putanga e whakau ana i te whanonga e whai ake nei:

  1. Ko te arorau kiritaki ka tautuhi ano i te matua IP.
  2. Ko te arorau a te kiritaki e tatari ana mo te tirohanga ara raraunga RX.
  3. Ko te arorau a te kiritaki ka tuku i nga angamaha i runga i te atanga TX MII me te tatari kia riro mai nga taapiri e rima ki runga i te atanga RX MII. Ka tukuna nga Hyperframes me te whiwhi i runga i te atanga MII e ai ki nga whakaritenga CPRI v7.0.
    Tuhipoka: Ko nga hoahoa CPRI e aro ana ki te 1.2, 2.4, 3, 4.9, 6.1, me te 9.8 Gbps reeti raina e whakamahi ana i te atanga 8b / 10b me nga hoahoa e aro ana ki te 10.1, 12.1 me 24.3 Gbps (me te kore RS-FEC) e whakamahi ana i te atanga MII. Ko tenei hoahoa exampKei roto he porotiti haerenga a tawhio noa ki te tatau i te roanga haerenga a tawhio noa mai i TX ki RX.
  4. Ka panuihia e te arorau a te kiritaki te uara torohū haerenga a tawhio noa, me te tirotiro i te ihirangi me te tika o nga raraunga anga whakamuri i te taha RX MII ina oti ana te kaute i te tatau torohū haerenga a tawhio noa.

Nga korero e pa ana

  • Ko nga korero a te CPRI
Hoahoa Pūmārō Example

Whakaahua 8. Hoahoa Pumau Exampte Hoahoa Poraka

intel F-Tile CPRI PHY FPGA IP Hoahoa Exampte piki 8

 

Tuhipoka

  1. Ko nga hoahoa CPRI me te 2.4/4.9/9.8 Gbps CPRI reiti raina whakamahi atanga 8b/10b me era atu hoahoa reiti raina CPRI katoa e whakamahi ana i te atanga MII.
  2. Ko nga hoahoa CPRI me te 2.4/4.9/9.8 Gbps CPRI reiti raina me 153.6 MHz karaka tohutoro whakawhiti me era atu reiti raina CPRI me 184.32 MHz.

Ko te F-Tile CPRI PHY Intel FPGA IP hoahoa taputapu matua exampKei roto i nga waahanga e whai ake nei:

  • F-Tile CPRI PHY Intel FPGA IP matua.
  • Paraka arorau a te kiritaki e whakaputa me te whiwhi waka.
  • porotiti haere huri noa.
  • IOPLL ki te whakaputa sampling karaka mo te arorau roanga i roto i te IP, me te waahanga porotiti haerenga huri noa i te papa whakamatautau.
  • Pūnaha PLL ki te whakaputa karaka pūnaha mo te IP.
  • Avalon®-MM pūwetewaehere wāhitau hei wetewete i te mokowā wāhitau whirihora anō mō ​​ngā kōwae CPRI, Transceiver, me Itarangi i te wā whakaurunga anō.
  • Ko nga puna me nga rangahau mo te kii mo te tautuhi me te aro turuki i nga karaka me etahi moka mana.
  • JTAG kaiwhakahaere e korero ana ki te Papatohu Pūnaha. Ka whakawhitiwhiti korero koe me te whakaaro a te kiritaki ma te Papatohu Pūnaha.
Tohu Atanga

Ripanga 5. Hoahoa Example Tohu Atanga

Waitohu Te aronga Whakaahuatanga
ref_clk100MHz Whakauru Karaka whakauru mo te uru TKT ki nga atanga whirihora katoa. Peia i te 100 MHz.
i_clk_ref[0] Whakauru Karaka tohutoro mo te PLL Pūnaha. Peia i te 156.25 MHz.
i_clk_ref[1] Whakauru Karaka tohutoro whakawhiti. Peia ki

• 153.6 MHz mo te reiti raina CPRI 1.2, 2.4, 3, 4.9, 6.1, me te 9.8 Gbps.

• 184.32 MHz mo nga reiti raina CPRI 10.1,12.1, me te 24.3 Gbps me te RS-FEC me te kore.
i_rx_rangatū[n] Whakauru Kaituku PHY whakauru raraunga rangatū.
o_tx_rangatū[n] Putanga Whakaputa PHY raraunga rangatū.
Hoahoa Example Rehita

Ripanga 6. Hoahoa Example Rehita

Tau Channel Wāhitau Paerewa (Wāhitau Paita) Momo Rēhita
 

 

0

 0x00000000 Ka rehitatia a CPRI PHY whirihora mo te hongere 0
0x00100000 Ko te whirihora a Ethernet ka rehita mo te hongere 0
0x00200000 Ka rehitatia te Whirihoranga Whakawhitiwhiti mo te Hongere 0
 

1(2)

 0x01000000 Ka rehitatia a CPRI PHY whirihora mo te hongere 1
0x01100000 Ko te whirihora a Ethernet ka rehita mo te hongere 1
0x01200000 Ka rehitatia te Whirihoranga Whakawhitiwhiti mo te Hongere 1
 

2(2)

 0x02000000 Ka rehitatia a CPRI PHY whirihora mo te hongere 2
0x02100000 Ko te whirihora a Ethernet ka rehita mo te hongere 2
0x02200000 Ka rehitatia te Whirihoranga Whakawhitiwhiti mo te Hongere 2
haere tonu…
Tau Channel Wāhitau Paerewa (Wāhitau Paita) Momo Rēhita
 

3(2)

 0x03000000 Ka rehitatia a CPRI PHY whirihora mo te hongere 3
0x03100000 Ko te whirihora a Ethernet ka rehita mo te hongere 3
0x03200000 Ka rehitatia te Whirihoranga Whakawhitiwhiti mo te Hongere 3

Ka rahuitia enei rehita ki te kore e whakamahia te hongere.

F-Tile CPRI PHY Intel FPGA IP Hoahoa Example Archives Aratohu Kaiwhakamahi

Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.

Intel Quartus Prime Putanga Putanga Matua IP Aratohu Kaiwhakamahi
21.2 2.0.0 F-Tile CPRI PHY Intel FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi

Tuhinga o mua mo te F-Tile CPRI PHY Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

Putanga Tuhinga Intel Quartus Prime Putanga Putanga IP Huringa
2021.10.04 21.3 3.0.0
  • He tautoko taapiri mo nga simulators hou i te waahanga: Nga Whakaritenga Pumau me nga Pūmanawa.
  • Ko nga waahanga kua whakahoutia i te waahanga: Whakataurite i te Hoahoa Exampte Testbench.
  • I whakahōuhia nga waahanga e whai ake nei me nga korero reiti raina hou:
    • Hoahoa Example Whakaahuatanga
    • Hoahoa whaihanga Example
    • Tohu Atanga
  • I whakahōuhia te wāhitau i te wāhanga: Hoahoa Example Rehita.
2021.06.21 21.2 2.0.0 Tukunga tuatahi.

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau he kawenga, he taunahatanga ranei a Intel i puta mai i te tono, i te whakamahi ranei i nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari i whakaaehia i roto i te tuhi a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei.
*Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

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intel F-Tile CPRI PHY FPGA IP Hoahoa Example [pdf] Aratohu Kaiwhakamahi
F-Tile CPRI PHY FPGA IP Hoahoa Example, PHY FPGA IP Hoahoa Example, F-Tile CPRI IP Hoahoa Example, IP Hoahoa Example, Hoahoa IP

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