F-Tile Interlaken Intel FPGA IP Hoahoa Example

Aratohu Timata Tere

Ko te F-Tile Interlaken Intel® FPGA IP matua e whakarato ana i te papa whakamatautau whaihanga. He hoahoa taputapu exampKo nga mea e tautoko ana i te whakahiato me nga whakamatautau taputapu ka waatea i roto i te putanga rorohiko Intel Quartus® Prime Pro Edition 21.4. Ina whakaputa koe i te hoahoa exampte, te ētita tawhā hanga aunoa i te files e tika ana ki te whaihanga, whakahiato, me te whakamatautau i te hoahoa.
Ko te papa whakamatautau me te hoahoa exampKa tautokohia e ia te NRZ me te PAM4 mo nga taputapu F-tile. Ko te F-Tile Interlaken Intel FPGA IP matua hanga hoahoa exampmo nga huinga tautoko e whai ake nei o te maha o nga huarahi me nga reeti raraunga.

IP Tautokohia nga Whakakotahitanga o te maha o nga huarahi me nga reiti Raraunga
Ko nga huinga e whai ake nei e tautokohia ana i roto i te putanga rorohiko Intel Quartus Prime Pro Edition 21.3. Ko etahi atu huinga katoa ka tautokohia i roto i te putanga a muri ake o te Intel Quartus Prime Pro Edition.

Te maha o nga huarahi	Reiti huarahi (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Ae	–	Ae	Ae	–
6	–	–	–	Ae	Ae
8	–	–	Ae	Ae	–
10	–	–	Ae	Ae	–
12	–	Ae	Ae	Ae	–

Whakaahua 1. Nga Waahi Whakawhanaketanga mo te Hoahoa Example

Tuhipoka: Ka watea te whakahiato me te whakamatautau i roto i te putanga rorohiko Intel Quartus Prime Pro Edition 21.4.
Ko te F-Tile Interlaken Intel FPGA IP hoahoa matua exampKei te tautoko a le i nga ahuatanga e whai ake nei:

• TX roto ki RX aratau loopback rangatū
• Ka whakaputa aunoa i nga putea rahi kua whakaritea
• Nga kaha ki te tirotiro i nga paatete taketake
• Te kaha ki te whakamahi i te Papatohu Pūnaha ki te tautuhi i te hoahoa mo te kaupapa whakamatautau ano

Whakaatu 2.High-level Block Hoahoa

Nga korero e pa ana

• F-Tile Interlaken Intel FPGA IP Aratohu Kaiwhakamahi
• F-Tile Interlaken Intel FPGA IP Release Notes

Nga Whakaritenga Pumau me nga Pūmanawa

Hei whakamatautau i te exampte hoahoa, whakamahia nga taputapu me nga rorohiko e whai ake nei:

• Putanga rorohiko Intel Quartus Prime Pro 21.3
• Papatohu Pūnaha
• Simulator Tautoko:
  • Synopsys* VCS*
  • Synopsys VCS MX
  • Siemens* EDA ModelSim* SE or Questa*

Tuhipoka:  Tautoko taputapu mo te hoahoa exampka watea i roto i te putanga rorohiko Intel Quartus Prime Pro Edition 21.4.

Te whakaputa i te Hoahoa

Whakaahua 3. Tikanga

A pee i enei mahi ki te whakaputa i te hoahoa example me te papa whakamatautau:

1. I roto i te rorohiko Intel Quartus Prime Pro Edition, pawhiria File ➤ Ruānuku Kaupapa Hou hei hanga kaupapa hou Intel Quartus Prime, paato ranei File ➤ Kaupapa Tuwhera hei whakatuwhera i tetahi kaupapa Intel Quartus Prime. Ka akiaki koe e te ruānuku ki te tautuhi i tetahi taputapu.
2. Tauwhāitihia te whanau taputapu Agilex ka tohua te taputapu whai F-Tile mo to hoahoa.
3. I roto i te Putumōhio IP, kimihia ka paato-rua F-Tile Interlaken Intel FPGA IP. Ka puta te matapihi rereke IP Hou.
4. Tauwhāitihia he ingoa taumata-runga mo to rereketanga IP ritenga. Ka tiakina e te ētita tawhā ngā tautuhinga rerekētanga IP i roto i te a file whakaingoatia .ip.
5. Pāwhiritia OK. Ka puta te ētita tawhā.

Whakaahua 4. Exampte Ripa Hoahoa

6. I runga i te ripa IP, whakapūtāhia ngā tawhā mō tō rerekētanga matua IP.
7. I te Exampte ripa Hoahoa, tohua te whiringa Whakamutunga ki te whakaputa i te papa whakamatautau.
Tuhipoka: Ko te kōwhiringa whakahiato mo te taputapu exampte hoahoa, ka waatea i roto i te putanga rorohiko Intel Quartus Prime Pro Edition 21.4.
8. Mo te Hōputu HDL Hangaia, kei te waatea nga whiringa Verilog me VHDL.
9. Pāwhiritia Hanga Exampte Hoahoa. Ko te Tohu Exampka puta te matapihi Design Directory.
10. Ki te hiahia koe ki te whakarerekē i te hoahoa exampte ara whaiaronga, ingoa ranei mai i nga taunoa kua whakaatuhia (ilk_f_0_example_design), tirotiro ki te ara hou ka pato i te hoahoa hou exampte ingoa whaiaronga.
11. Paatohia te OK

Tuhipoka: I roto i te F-Tile Interlaken Intel FPGA IP hoahoa exampNa, he SystemPLL he mea hanga aunoa, ka hono ki te F-Tile Interlaken Intel FPGA IP matua. Ko te ara aroākapa SystemPLL i te hoahoa exampko:

example_design.test_env_inst.test_dut.dut.pll

Ko te SystemPLL i roto i te hoahoa exampHe rite te karaka tohutoro 156.26 MHz ki te Kaituku.

Hanganga Whaiaronga

Ko te F-Tile Interlaken Intel FPGA IP matua e whakaputa ana i nga mea e whai ake nei files mo te hoahoa example:
Whakaatu 5. Hanganga Whaiaronga

Ripanga 2. Hoahoa Pūmārō Example File Whakaahuatanga
Ko enei files kei roto i teample_installation_dir>/ilk_f_0_example_design whaiaronga.

File Nga Ingoa	Whakaahuatanga
example_design.qpf	Kaupapa Intel Quartus Prime file.
example_design.qsf	Tautuhinga kaupapa Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	Te herenga Hoahoa Synopsys file. Ka taea e koe te kape me te whakarereke mo to ake hoahoa.
sysconsole_testbench.tcl	Matua file mo te uru atu ki te Papatohu Pūnaha

Tuhipoka: Tautoko taputapu mo te hoahoa exampka watea i roto i te putanga rorohiko Intel Quartus Prime Pro Edition 21.4.

Ripanga 3. Taumatau File Whakaahuatanga

Tenei file kei roto i teample_installation_dir>/ilk_f_0_example_design/ example_design/rtl whaiaronga.

File Ingoa	Whakaahuatanga
top_tb.sv	Te pae whakamatautau taumata-runga file.

Ripanga 4. Nga Tuhituhi Whakamatau

Ko enei files kei roto i teample_installation_dir>/ilk_f_0_example_design/ exampwhaiaronga le_design/testbench

File Ingoa	Whakaahuatanga
run_vcs.sh	Ko te tuhinga Synopsys VCS hei whakahaere i te papa whakamatautau.
run_vcsmx.sh	Ko te tuhinga Synopsys VCS MX hei whakahaere i te papa whakamatautau.
run_mentor.tcl	Ko te Siemens EDA ModelSim SE ko Questa tuhinga ranei hei whakahaere i te papa whakamatautau.

Whakataurite i te Hoahoa Exampte Testbench

Whakaatu 6. Tikanga

A pee i enei taahiraa hei whakatauira i te papa whakamatautau:

1. I te whakahau whakahau, huri ki te whaiaronga whaihanga testbench. Ko te ara whaiarongaample_installation_dir>/example_design/whakamatautau.
2. Whakahaerehia te tuhinga whaihanga mo te simulator tautoko e pai ana koe. Ka whakahiato, ka whakahaeretia e te tuhinga te papa whakamatautau i roto i te simulator. Me tirohia e to tuhinga he rite nga tatau SOP me te EOP i muri i te otinga o te whaihanga.

Ripanga 5. Nga Tikanga ki te Whakahaere Whakatau

Simulator	Tohutohu
VCS	I roto i te raina whakahau, pato:   sh run_vcs.sh
VCS MX	I roto i te raina whakahau, pato:   sh run_vcsmx.sh
ModelSim SE ko Questa ranei	I roto i te raina whakahau, pato:   vsim -do run_mentor.tcl Mena he pai ki a koe ki te whakataurite me te kore e kawe ake i te ModelSim GUI, pato:   vsim -c -do run_mentor.tcl

3. Tātarihia ngā hua. He whaihanga angitu te tuku me te tango i nga paatete, me te whakaatu i te "TEST PASSED".

Ko te papa whakamatautau mo te hoahoa exampKa oti e ia nga mahi e whai ake nei:

• Ka whakaara ake i te matua F-Tile Interlaken Intel FPGA IP.
• Ka tā i te tūnga PHY.
• Ka taki i te tukutahinga metaframe (SYNC_LOCK) me nga rohe kupu (paraka) (WORD_LOCK).
• Ka tatari kia maukatihia nga huarahi takitahi me te whakatiaro.
• Ka timata te tuku paakete.
• Ka taki i nga tatauranga mokete:
  • Nga hapa CRC24
  • Nga SOP
  • Nga EOP

Ko nga s e whai ake neiampKo te putanga e whakaatu ana i te oma whakamatautau whaihanga angitu:

Te whakahiato i te Hoahoa Example

1. Whakaritea te exampKua oti te whakatipuranga hoahoa.
2. I roto i te rorohiko Intel Quartus Prime Pro Edition, whakatuwheratia te kaupapa Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. I te tahua Tukatuka, pawhiria te Tīmata Whakahiato.

Hoahoa Example Whakaahuatanga

Ko te hoahoa exampe whakaatu ana i nga mahi o te matua IP Interlaken.

Hoahoa Exampte Waehanga

Ko te exampKo te hoahoa e hono ana i te punaha me nga karaka tohutoro PLL me nga waahanga hoahoa e hiahiatia ana. Ko te exampKa whirihora e te hoahoa te matua IP i roto i te aratau loopback o roto me te whakaputa i nga paatete i runga i te atanga whakawhiti raraunga kaiwhakamahi IP matua TX. Ka tukuna e te matua IP enei paakete i runga i te ara takahuri-a-roto na roto i te whakawhiti.
I muri i te whiwhinga o te kaiwhiwhi matua IP i nga paatete i runga i te ara takahuri, ka tukatukahia e ia nga paatete Interlaken ka tukuna ki runga i te atanga whakawhiti raraunga kaiwhakamahi RX. Ko te exampKa tirohia e te hoahoa i whiwhi nga paakete me te tuku i te rite.
Ko te F-Tile Interlaken Intel IP hoahoa exampKei roto i nga waahanga e whai ake nei:

1. F-Tile Interlaken Intel FPGA IP matua
2. Kaihanga Packet me te Kaitaki Packet
3. Tohutoro F-Tapa me te Pūnaha PLL Karaka Intel FPGA IP matua

Tohu Atanga

Ripanga 6. Hoahoa Example Tohu Atanga

Ingoa Tauranga	Te aronga	Whānui (Moka)	Whakaahuatanga
mgmt_clk	Whakauru	1	Tāuru karaka Pūnaha. Me 100 MHz te auau karaka.
pll_ref_clk	Whakauru	1	Karaka tohutoro whakawhiti. Ka peia te RX CDR PLL.
rx_pin	Whakauru	Te maha o nga huarahi	Kaiwhiwhi SERDES titi raraunga.
tx_pin	Putanga	Te maha o nga huarahi	Tukua te titi raraunga SERDES.
rx_pin_n(1)	Whakauru	Te maha o nga huarahi	Kaiwhiwhi SERDES titi raraunga.
tx_pin_n(1)	Putanga	Te maha o nga huarahi	Tukua te titi raraunga SERDES.
mac_clk_pll_ref	Whakauru	1	Me peia tenei tohu e te PLL me te whakamahi i te puna karaka ano e peia ana te pll_ref_clk. Kei te waatea noa tenei tohu i roto i nga rereketanga taputapu aratau PAM4.
usr_pb_reset_n	Whakauru	1	Tautuhi ano o te punaha.

(1) Kei te waatea noa i nga momo PAM4.

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau he kawenga, he taunahatanga ranei a Intel i puta mai i te tono, i te whakamahi ranei i nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari i whakaaehia i roto i te tuhi a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei.
*Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

Rēhita Mapi

Tuhipoka:

• Hoahoa ExampKa timata te wahitau rehita ki te 0x20** ka timata te wahitau rehitatanga matua o Interlaken IP ki te 0x10**.
• Ka timata te wahitau rehita F-tile PHY ki te 0x30** ka timata te wahitau rehita F-tile FEC ki te 0x40**. Kei te waatea noa te rehita FEC i te aratau PAM4.
• Waehere uru: RO—Panui Anake, me RW—Panui/Tuhia.
• Ka panuihia e te papatohu punaha te hoahoa exampKa rehita me te ripoata te mana whakamatautau i runga i te mata.

Ripanga 7. Hoahoa Example Mahere Rehita

Whangai	Ingoa	Urunga	Whakaahuatanga
8'h00	Kua rahuitia
8'h01	Kua rahuitia
8'h02	Tautuhi PLL Pūnaha	RO	Ko nga moka e whai ake nei e tohu ana i te tono tautuhi PLL punaha me te whakahohe i te uara: • Moka [0] – sys_pll_rst_req • Moka [1] – sys_pll_rst_en
8'h03	RX arai tiaaro	RO	E tohu ana i te tirohanga ara RX.
8'h04	WORD raka	RO	[NUM_LANES–1:0] – Tautuhinga rohenga kupu (poraka).
8'h05	Kua maukati te tukutahi	RO	[NUM_LANES–1:0] – Tukutahi Metaframe.
8'h06 - 8'h09	Tatau hapa CRC32	RO	Ka tohu i te tatau hapa CRC32.
8'h0A	Tatau hapa CRC24	RO	Ka tohu i te tatau hapa CRC24.
8'h0B	Waitohu Puawai/Tararo	RO	Ko nga moka e whai ake nei e tohu ana: • Moka [3] – TX tohu rerenga wai • Moka [2] – Tohu waipuke TX • Moka [1] – Tohu waipuke RX
8'h0C	tatau SOP	RO	Ka tohu te maha o te SOP.
8'h0D	tatau EOP	RO	Ka tohu te maha o te EOP
8'h0E	Tatau hapa	RO	Ka tohu i te maha o nga hapa e whai ake nei: • Te ngaronga o te tirohanga ara • Kupu whakahaere ture • He tauira anga ture kore • Kei te ngaro te tohu SOP, EOP ranei
8'h0F	tuku_raraunga_mm_clk	RW	Tuhia te 1 ki te moka [0] kia taea ai te tohu whakaputa.
8'h10	Hapa kaitaki		Ka tohu i te hapa kaitaki. (Hapa raraunga SOP, hapa tau hongere, he hapa raraunga PLD)
8'h11	Maukati PLL Pūnaha	RO	Ko te bit [0] he tohu maukati PLL.
8'h14	Tatau TX SOP	RO	E tohu ana i te maha o te SOP i hangaia e te kaihanga kete.
8'h15	TX EOP tatau	RO	E tohu ana i te maha o te EOP i hangaia e te kaihanga kete.
8'h16	Mōkete haere tonu	RW	Tuhia te 1 ki te moka [0] kia taea ai te paatete tonu.
haere tonu…

Whangai	Ingoa	Urunga	Whakaahuatanga
8'h39	tatau hapa ECC	RO	Ka tohu te maha o nga hapa ECC.
8'h40	Kua whakatikahia e te ECC te tatau hapa	RO	Ka tohu i te maha o nga hapa ECC kua whakatikahia.
8'h50	tile_tx_rst_n	WO	Tautuhi Tile ki SRC mo TX.
8'h51	tile_rx_rst_n	WO	Tautuhi Tile ki SRC mo RX.
8'h52	tile_tx_rst_ack_n	RO	Ka whakaaehia te tautuhi taapiri mai i te SRC mo TX.
8'h53	tile_rx_rst_ack_n	RO	Whakaaehia te tautuhi taapiri mai i te SRC mo RX.

Tautuhi Anō

I roto i te F-Tile Interlaken Intel FPGA IP matua, ka timata koe i te tautuhi (reset_n=0) ka pupuri kia whakahokia mai e te matua IP he tohu tautuhi (reset_ack_n=0). I muri i te tangohanga o te tautuhi (reset_n=1), ka hoki ano te tohu tautuhi ki tona ahuatanga tuatahi
(reset_ack_n=1). I roto i te hoahoa exampNa, ko te rehita rst_ack_sticky e pupuri ana i te korero whakamohiotanga katahi ka puta te tango i te tautuhi (reset_n=1). Ka taea e koe te whakamahi tikanga rereke e pai ana ki o hiahia hoahoa.

Hiranga: I roto i tetahi ahuatanga e hiahiatia ana te hurihanga rangatū o roto, me tuku wehe te TX me te RX o te F-tile i roto i te raupapa motuhake. Tirohia te tuhinga papatohu punaha mo etahi atu korero.

Whakaatu 7. Tautuhi Rarangi i te Aratau NRZ

Whakaatu 8. Tautuhi Rarangi i te Aratau PAM4

F-Tile Interlaken Intel FPGA IP Hoahoa Example Archives Aratohu Kaiwhakamahi

Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.

Intel Quartus Prime Putanga	Putanga Matua IP	Aratohu Kaiwhakamahi
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi

Tuhinga Tuhinga History mo F-Tile Interlaken Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

Putanga Tuhinga	Intel Quartus Prime Putanga	Putanga IP	Huringa
2021.10.04	21.3	3.0.0	• He tautoko taapiri mo nga huinga reiti huarahi hou. Mo etahi atu korero, tirohia Ripanga: Whakakotahitanga Tautoko IP o te maha o nga huarahi me te tere Raraunga. • Whakahoutia te rarangi simulator tautoko i te waahanga: Nga Whakaritenga Pumau me nga Pūmanawa. • Kua taapirihia nga rehita tautuhi hou ki te waahanga: Rēhita Mapi.
2021.06.21	21.2	2.0.0	Tukunga tuatahi.

Tuhinga / Rauemi

intel F-Tile Interlaken Intel FPGA IP Hoahoa Example [pdf] Aratohu Kaiwhakamahi F-Tile Interlaken Intel FPGA IP Hoahoa Example, F-Tile, Interlaken Intel FPGA IP Design Example, Intel FPGA IP Hoahoa Example, IP Hoahoa Example, Hoahoa Example

Tohutoro

• Pukapuka Kaiwhakamahi