F-Tile DisplayPort FPGA IP Hoahoa Example
Aratohu Kaiwhakamahi
F-Tile DisplayPort FPGA IP Hoahoa Example
Kua whakahoutia mo Intel® Quartus® Prime Design Suite: 22.2 IP Putanga: 21.0.1
DisplayPort Intel FPGA IP Hoahoa Exampte Aratohu Timata Tere
Kei roto i nga taputapu DisplayPort Intel® F-tile he papa whakamatautau me tetahi hoahoa taputapu e tautoko ana i te whakahiato me te whakamatautau taputapu FPGA IP hoahoa examphe utu mo Intel Agilex™
Ko te DisplayPort Intel FPGA IP e tuku ana i nga tauira hoahoa e whai ake neiampiti:
- Whakaaturanga SST whakarara whakarara whakamuri karekau he kōwae Whakaora Karaka Pika (PCR).
- Whakaaturanga SST whakarara whakarara ki te Atanga Ataata AXIS
Ina hanga e koe he hoahoa exampte, te ētita tawhā hanga aunoa i te files e tika ana ki te whaihanga, whakahiato, me te whakamatautau i te hoahoa i roto i te taputapu.
Whakaahua 1. Whanaketanga Stages
Nga korero e pa ana
- Whakaaturanga Whakaaturanga Intel FPGA IP Aratohu Kaiwhakamahi
- Heke ki Intel Quartus Prime Pro Edition
Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau he kawenga, he taunahatanga ranei a Intel i puta mai i te tono, i te whakamahi ranei i nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari i whakaaehia i roto i te tuhi a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei.
*Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.
ISO 9001:2015 Kua Rehitatia
1.1. Hanganga Whaiaronga
Whakaatu 2. Hanganga Whaiaronga
Ripanga 1. Hoahoa Exampte Waehanga
| Kōpaki | Files |
| rtl/matua | dp_core.ip |
| dp_rx . ip | |
| dp_tx . ip | |
| rtl/rx_phy | dp_gxb_rx/ ((Paraka hangahanga DP PMA UX) |
| dp_rx_data_fifo . ip | |
| rx_top_phy . sv | |
| rtl/tx_phy | dp_gxb_rx/ ((Paraka hangahanga DP PMA UX) |
| dp_tx_data_fifo.ip | |
| dp_tx_data_fifo.ip |
1.2. Nga Whakaritenga Pumau me nga Pūmanawa
Ka whakamahia e Intel nga taputapu me nga rorohiko e whai ake nei hei whakamatautau i te hoahoa o muaample:
Pūmārō
- Intel Agilex I-Series Development Kit
- Whakaaturanga Puna GPU
- Totohu Tauranga Whakaatu (Aroturuki)
- Kaari tamahine Bitec DisplayPort FMC Revision 8C
- Tauira Whakaaturanga
Pūmanawa
- Intel Quartus® Prime
- Synopsys* VCS Simulator
1.3. Te whakaputa i te Hoahoa
Whakamahia te DisplayPort Intel FPGA IP ētita tawhā i roto i te rorohiko Intel Quartus Prime hei whakaputa i te hoahoa o muaample.
Whakaatu 3. Te Whakaputa i te Rere Hoahoa
- Tīpakohia nga Utauta ➤ IP Catalog, ka kowhiria te Intel Agilex F-tile hei whanau taputapu e whaaia ana.
Tuhipoka: Ko te hoahoa exampKa tautoko noa i nga taputapu Intel Agilex F-tile. - I roto i te Putumōhio IP, kimihia ka paato-rua DisplayPort Intel FPGA IP. Ka puta te matapihi Rerekē IP Hou.
- Tauwhāitihia he ingoa taumata-runga mo to rereketanga IP ritenga. Ka tiakina e te ētita tawhā ngā tautuhinga rerekētanga IP i roto i te a file whakaingoatia .ip.
- Tīpakohia he taputapu Intel Agilex F-tile i te mara Pūrere, pupuri ranei i te whiringa taputapu rorohiko Intel Quartus Prime taunoa.
- Pāwhiritia OK. Ka puta te ētita tawhā.
- Whirihorahia nga tawhā e hiahiatia ana mo te TX me te RX.
- I raro i te Design Exampi te ripa, tohua Whakaaturanga SST Whakarara Whakamuri Kore he PCR.
- Tīpakohia te Whakaakoranga hei whakaputa i te pae whakamatautau, ka kowhiria te Synthesis hei whakaputa i te hoahoa taputapu example. Me whiriwhiri koe i tetahi o enei whiringa hei whakaputa i te hoahoa o muaample files. Mena ka kowhiria e koe nga mea e rua, ka roa ake te wa whakatipuranga.
- Mo te Kete Whanaketanga Whainga, tohua Intel Agilex I-Series SOC Development Kit. Na tenei ka huri te taputapu i tohua i te taahiraa 4 kia rite ki te taputapu kei runga i te kete whanaketanga. Mo Intel Agilex I-Series SOC Development Kit, ko te taputapu taunoa ko AGIB027R31B1E2VR0.
- Pāwhiritia Whakaputa Exampte Hoahoa.
1.4. Whakatauhanga i te Hoahoa
Ko te DisplayPort Intel FPGA IP hoahoa exampKa whakatauirahia e te testbench he hoahoa loopback rangatū mai i te tauira TX ki te tauira RX. Ko te tauira whakaputa tauira ataata o roto ka peia te tauira DisplayPort TX ka hono te putanga ataata tauira RX ki nga kaitaki CRC i te papa whakamatautau.
Whakaatu 4. Rere Whakatau Hoahoa
- Haere ki te kōpaki simulator Synopsys ka kowhiri i te VCS.
- Whakahaere hōtuhi whaihanga.
Puna vcs_sim.sh - Ka mahia e te tuhinga te Quartus TLG, ka whakahiato me te whakahaere i te papa whakamatautau i roto i te simulator.
- Tātarihia te hua.
Ka mutu te whaihanga angitu me te whakataurite o te Puna me te Sink SRC.
1.5. Te whakahiato me te whakamatautau i te hoahoa
Whakaatu 5. Te whakahiato me te Whakahoahoa i te Hoahoa
Hei whakahiato me te whakahaere i tetahi whakamatautau whakaaturanga mo te taputapu exampte hoahoa, whai i enei mahi:
- Me whakarite taputapu exampKua oti te whakatipuranga hoahoa.
- Whakarewahia te rorohiko Intel Quartus Prime Pro Edition ka tuwhera / quartus/agi_dp_demo.qpf.
- Pāwhiritia te Tukatuka ➤ Tīmata te Whakaemi.
- Whai muri i te whakahiato angitu, ka hangaia e te rorohiko Intel Quartus Prime Pro Edition he .sof file i roto i to whaiaronga kua tohua.
- Tūhonohia te tūhono DisplayPort RX i runga i te kaari tamahine Bitec ki tetahi puna WhakaatuPort o waho, penei i te kaari whakairoiro i runga PC.
- Tūhonohia te tūhono DisplayPort TX i runga i te kāri tamahine Bitec ki te taputapu totohu DisplayPort, penei i te kaitirotiro ataata, i te kaitirotiro PC ranei.
- Me mohio kei te noho taunoa nga huringa katoa o te papa whanaketanga.
- Whirihorahia te taputapu Intel Agilex F-Tile i tohua i runga i te papa whanaketanga ma te whakamahi i te .sof i hangaia file (Nga Utauta ➤ Kaiwhakataka).
- Ko te taputapu totohu DisplayPort e whakaatu ana i te ataata i hangaia mai i te puna ataata.
Nga korero e pa ana
Intel Agilex I-Series FPGA Development Kit Aratohu Kaiwhakamahi/
1.5.1. Te whakahou i te ELF File
Ma te taunoa, ko te ELF file ka hangaia ina whakaputa koe i te hoahoa hihiri example.
Engari, i etahi wa, me whakahou e koe te ELF file ki te whakarereke koe i te rorohiko file whakahou ranei i te dp_core.qsys file. Te whakahou i te dp_core.qsys file whakahōu i te .sopcinfo file, e hiahia ana koe ki te whakahou i te ELF file.
- Haere ki /pūmanawa me te whakatika i te waehere mēnā e tika ana.
- Haere ki /whakatuhi ka mahia te tuhinga hanga e whai ake nei: puna build_sw.sh
• I te Matapihi, rapu me te whakatuwhera i te Nios II Command Shell. I roto i te Nios II Command Shell, haere ki /whakatuhi ka mahia te puna build_sw.sh.
Tuhipoka: Hei whakahaere i te tuhinga hanga i runga Windows 10, me hiahia to punaha ki nga punaha Windows mo Linux (WSL). Mo etahi atu korero mo te whakaurunga WSL, tirohia te Nios II Software Developer Handbook.
• I runga i te Linux, whakarewahia te Kaihoahoa Platform, ka whakatuwhera i nga Utauta ➤ Nios II Command Shell. I roto i te Nios II Command Shell, haere ki /whakatuhi ka mahia te puna build_sw.sh. - Me whakarite he .elf file ka hangaia i roto /pūmanawa/ dp_demo.
- Tikiake i te .elf i hangaia file ki te FPGA me te kore e whakahiato i te .sof file ma te whakahaere i te tuhinga e whai ake nei: nios2-download /pūmanawa/dp_demo/*.elf
- Panahia te patene tautuhi ki te papa FPGA kia whai mana ai te rorohiko hou.
1.6. DisplayPort Intel FPGA IP Hoahoa Exampte Tawhā
Ripanga 2. DisplayPort Intel FPGA IP Design Exampte herenga QSF mo Intel Agilex Ftile Device
| QSF Herenga |
Whakaahuatanga |
| huinga_whakamahinga_ao -ingoa VERILOG_MACRO “__DISPLAYPORT_tautoko__=1” |
Mai i te Quartus 22.2 haere ake, ka hiahiatia tenei herenga QSF kia taea ai te rere a DisplayPort ritenga SRC (Kaiwhakahaere Tautuhi Ngawari) |
Ripanga 3. DisplayPort Intel FPGA IP Design Example Tawhā mo te Pūrere Intel Agilex F-tile
| Tawhā | Uara | Whakaahuatanga |
| Hoahoa Wātea Example | ||
| Tohua Hoahoa | •Karekau •DisplayPort SST Parallel Loopback kaore he PCR •DisplayPort SST Parallel Loopback me te Atanga Ataata AXIS |
Tīpakohia te hoahoa exampkia hangaia. •Kore: No hoahoa exampKei te waatea te mo te kowhiringa tawhā o naianei. •DisplayPort SST Parallel Loopback kahore PCR: Ko tenei hoahoa exampe whakaatu ana i te whakarara whakarara mai i te totohu DisplayPort ki te puna WhakaatuPort me te kore he kōwae Whakaora Karaka Pika (PCR) ina ka whakahoe koe i te tawhā Tauranga Tauranga Whakaaturanga Ataata. •DisplayPort SST Parallel Loopback with AXIS Video Interface: Ko tenei hoahoa exampe whakaatu ana i te whakarara whakarara mai i te totohu DisplayPort ki te puna WhakaatuPort me te atanga Ataata AXIS ina Whakahohehia nga Kawa Raraunga Ataata Hohe kua tautuhia ki te AXIS-VVP Katoa. |
| Hoahoa Example Files | ||
| whaihanga | Kei, Weto | Tahurihia tenei whiringa ki te whakaputa i nga mea e tika ana files mo te papa whakamatautau whaihanga. |
| Te whakahiato | Kei, Weto | Tahurihia tenei whiringa ki te whakaputa i nga mea e tika ana files mo Intel Quartus Prime whakahiato me te hoahoa taputapu. |
| Hōputu HDL Hangaia | ||
| Whakaputa File Whakahōputu | Verilog, VHDL | Tīpakohia te whakatakotoranga HDL e pai ana koe mo te hoahoa o muaample filewhakatakotoria. Tuhipoka: Ma tenei whiringa anake e whakatau te whakatakotoranga mo te IP taumata teitei i hangaia files. Ko era atu katoa files (hei tauiraample testbenches me te taumata o runga files mo te whakaaturanga taputapu) kei te whakatakotoranga Verilog HDL. |
| Kete Whanaketanga Whainga | ||
| Whiriwhiria te Poari | •Kaore he Kete Whakawhanaketanga •Intel Agilex I-Series Kete Whakawhanaketanga |
Tīpakohia te papa mo te hoahoa kua whakariteaample. |
| Tawhā | Uara | Whakaahuatanga |
| •Kaore he Kete Whakawhanaketanga: Ko tenei kowhiringa ka aukati i nga waahanga taputapu katoa mo te hoahoa o muaample. Ka tautuhia e te P matua nga mahi titi katoa ki nga titi mariko. •Kei Whakawhanaketanga FPGA Intel Agilex I-Series: Ko tenei whiringa ka kowhiri aunoa i te taputapu whaainga o te kaupapa kia rite ki te taputapu kei runga i tenei kete whanaketanga. Ka taea e koe te huri i te taputapu whaainga ma te whakamahi i te tawhā Hurihia te Pūrere Target mena he rereke nga taputapu o to arotake poari. Ko te matua IP e whakatakoto ana i nga taumahi titi katoa e ai ki te kete whanaketanga. Tuhipoka: Hoahoa Tuatahi ExampKaore i te manatokohia te mahi i runga i nga taputapu i tenei tukunga Quartus. • Kete Whanaketanga Ritenga: Ma tenei whiringa ka taea te hoahoa o muaampkia whakamatauria ki te kete whanaketanga tuatoru me te Intel FPGA. Ka hiahia pea koe ki te whakarite i nga taumahi titi ki a koe ake. |
||
| Pūrere Whāinga | ||
| Hurihia te Pūrere Target | Kei, Weto | Whakakāhia tēnei kōwhiringa ka kōwhiri i te momo taputapu pai ake mo te kete whanaketanga. |
Hoahoa Loopback Whakarara Examples
Ko te DisplayPort Intel FPGA IP hoahoa exampKa whakaatuhia e matou te hurihanga whakarara mai i te tauira DisplayPort RX ki te tauira DisplayPort TX kaore he waahanga Whakaora Karaka Pika (PCR).
Ripanga 4. DisplayPort Intel FPGA IP Design Example mo te Pūrere Intel Agilex F-tile
| Hoahoa Example | Tohunga | Reiti Raraunga | Aratau Channel | Momo Whakamuri |
| Whakaaturanga SST whakarara whakarara whakamuri karekau he PCR | Tauranga Whakaatu SST | RBR, HRB, HRB2, HBR3 | Simplex | Whakarara kore PCR |
| Whakaaturanga SST whakarara whakarara ki te Atanga Ataata AXIS | Tauranga Whakaatu SST | RBR, HRB, HRB2, HBR3 | Simplex | Whakarara ki te Atanga Ataata AXIS |
2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Hoahoa Ngā āhuatanga
Ko te SST whakarara hoahoa loopback exampE whakaatu ana te tukunga o te awa ataata kotahi mai i te totohu DisplayPort ki te puna DisplayPort.
Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. *Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.
ISO 9001:2015 Kua Rehitatia
Whakaahua 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback kahore PCR
- I roto i tenei momo rereke, ka kaina te tawhā o te puna DisplayPort, TX_SUPPORT_IM_ENABLE, ka whakamahia te atanga atahanga ataata.
- Ka whiwhi te totohu DisplayPort i te riipene ataata me te ororongo mai i te puna ataata o waho penei i te GPU ka wetewetehia ki te atanga ataata whakarara.
- Ko te putanga ataata totohu o DisplayPort ka peia tika te atanga ataata puna DisplayPort me te whakawaehere ki te hononga matua DisplayPort i mua i te tuku ki te aroturuki.
- Ka peia e te IOPLL te totohu DisplayPort me nga karaka ataata puna i te auau kua whakaritea.
- Mena ka whirihorahia te totohu DisplayPort me te tawhā MAX_LINK_RATE o te puna ki te HBR3 me te PIXELS_PER_CLOCK ki te Quad, ka rere te karaka ataata ki te 300 MHz hei tautoko i te reiti pika 8Kp30 (1188/4 = 297 MHz).
Whakaatu 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback with AXIS Video Atanga
- I roto i tenei momo rereke, ko te puna Whakaaturanga me te tawhā totohu, tohua te AXIS-VVP FULL i roto i te WHAKAMAHI KAWA KAWA RARAUNGA VIDEO ACTIVE kia taea ai te Atanga Raraunga Ataata Tuaka.
- Ka whiwhi te totohu DisplayPort i te riipene ataata me te ororongo mai i te puna ataata o waho penei i te GPU ka wetewetehia ki te atanga ataata whakarara.
- Ko te DisplayPort Sink ka huri i te roma raraunga ataata ki nga raraunga ataata tuaka ka peia te atanga raraunga ataata tuaka puna DisplayPort ma te VVP Video Frame Buffer. Ko te Puna Whakaaturanga ka huri i nga raraunga ataata tuaka ki te hono matua DisplayPort i mua i te tuku ki te aroturuki.
- I roto i tenei momo hoahoa, e toru nga karaka ataata matua, ara rx/tx_axi4s_clk, rx_vid_clk, me tx_vid_clk. Ko te axi4s_clk ka rere i te 300 MHz mo nga waahanga AXIS e rua i te Puna me te Totohu. Ko te rx_vid_clk e whakahaere ana i te DP Sink Video pipeline i te 300 MHz (hei tautoko i tetahi whakataunga tae atu ki te 8Kp30 4PIPs), i te wa e whakahaere ana a tx_vid_clk i te DP Source Video pipeline i te auau o te Karaka Pika (wehea e nga PIP).
- Ko tenei momo hoahoa ka whirihora aunoa i te auau tx_vid_clk na roto i te kaupapa I2C ki te SI5391B OSC i runga i te papa ka kitea e te hoahoa he huringa i roto i te taumira.
- Ko tenei momo hoahoa ka whakaatu noa i te maha o nga whakataunga kua tautuhia i mua i te rorohiko WhakaatuPort, ara:
— 720p60, RGB
— 1080p60, RGB
— 4K30, RGB
— 4K60, RGB
2.2. Kaupapa Karaka
Ko te kaupapa karaka e whakaatu ana i nga rohe karaka i roto i te hoahoa DisplayPort Intel FPGA IP example.
Whakaahua 8. Intel Agilex F-tile DisplayPort Transceiver kaupapa karaka
Ripanga 5. Waitohu Kaupapa Karaka
| Karaka i te hoahoa |
Whakaahuatanga |
| SysPLL refclk | Karaka tohutoro PLL Pūnaha F-tile he karaka karaka ka wehea e te Pūnaha PLL mo taua auau putanga. I roto i tenei hoahoa exampKo te system_pll_clk_link me te rx/tx refclk_link he rite te 150 MHz SysPLL refclk. |
| Karaka i te hoahoa | Whakaahuatanga |
| Me he karaka rere kore utu e hono ana mai i te titi karaka tohutoro tohutoro kua whakatapua ki te tauranga karaka whakauru o Tohutoro me te Pūnaha PLL Karaka IP, i mua i te hono i te tauranga whakaputa e rite ana ki a DisplayPort Phy Top. Tuhipoka: Mo tenei hoahoa exampte, whirihora Karaka Kaiwhakahaere GUI Si5391A OUT6 ki 150 MHz. |
|
| pūnaha pll clk hono | Ko te iti o te auau putanga PLL Pūnaha hei tautoko i te reiti Whakaaturanga katoa ko te 320 MHz. Ko tenei hoahoa exampKa whakamahia e ia te 900 MHz (te teitei) te auau whakaputa kia taea ai e SysPLL refclk te tiri ki rx/tx refclk_link ko 150 MHz. |
| rx_cdr_refclk_link / tx_pll_refclk_link | Rx CDR me Tx PLL Hononga refclk i whakaritea ki te 150 MHz hei tautoko i nga reeti raraunga Whakaaturanga katoa. |
| rx_ls_clkout / tx_ls_clkout | Whakaaturanga Hononga Tere Karaka ki te karaka DisplayPort IP matua. Ko te auau e rite ana ki te Raraunga Raraunga wehewehe ki te whanui raraunga whakarara. Example: Auautanga = reeti raraunga / whanui raraunga = 8.1G (HBR3) / 40 paraka = 202.5 MHz |
2.3. Tauranga Whakamatau
Ka whakatairitehia e te papapae whakamatautau whaihanga te whakamuri rangatū WhakaatuPort TX ki RX.
Whakaatu 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Poraka Hoahoa
Ripanga 6. Nga Waenga Whakamatau
| Waehanga | Whakaahuatanga |
| Kaihanga Tauira Ataata | Ka hangaia e tenei kaihanga nga tauira pae tae ka taea e koe te whirihora. Ka taea e koe te whakarite i te waa whakatakotoranga ataata. |
| Mana Whakamatau | Ko tenei poraka e whakahaere ana i te raupapa whakamatautau o te whaihanga me te whakaputa i nga tohu whakaoho e tika ana ki te TX matua. Ka panuihia e te paraka whakahaere whakamatautau te uara CRC mai i te puna me te totohu hei whakataurite. |
| RX Hononga Tere Karaka Karaka Takitaki | Ka tirohia e tenei kaitaki mena ka rite te reeti karaka i whakahokia mai e te RX ki te reeti raraunga e hiahiatia ana. |
| TX Hononga Tere Karaka Kaitaki Auautanga | Ka tirohia e tenei kaitaki mena ka rite te reeti karaka i whakahokia mai e te kaiwhakawhitiwhiti TX ki te reeti raraunga e hiahiatia ana. |
Ka mahia e te papa whakamatautau whaihanga nga whakamana e whai ake nei:
Ripanga 7. Whakaaturanga Whakataunga
| Paearu Whakamatau |
Manatokonga |
| • Whakangungu Hononga i te Raraunga Raraunga HBR3 • Panuitia nga rehitatanga DPCD kia tirohia mena ka whakatauhia e te Tūnga DP me te ine i te auau TX me te RX Hononga Tere. |
Ka whakauru i te Kaitaki Auau ki te ine i te Tere Hononga putanga auau o te karaka i te TX me te RX transceiver. |
| • Whakahaere tauira ataata mai i TX ki RX. • Manatokohia te CRC mo te puna me te totohu kia tirohia mena he rite |
• Ka hono i te kaihanga tauira ataata ki te Whakaaturanga Puna hei whakaputa i te tauira ataata. • Ka panuihia e te mana Testbench te puna me te Sink CRC mai i nga rehita DPTX me DPRX me te whakataurite kia rite nga uara CRC e rua. Tuhipoka: Hei whakarite kia tatauhia te CRC, me whakaahei koe i te tawhā aunoatanga whakamātautau Tautoko CTS. |
Tuhinga Tuhinga History mo F-Tile DisplayPort Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi
| Putanga Tuhinga | Intel Quartus Prime Putanga | Putanga IP | Huringa |
| 2022.09.02 | 22. | 20.0.1 | •I hurihia te taitara tuhinga mai i DisplayPort Intel Agilex F-Tile FPGA IP Design Exampte Aratohu Kaiwhakamahi ki F-Tile DisplayPort Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi. •Whakahohe AXIS Video Design Exampte rereke. •I tangohia te hoahoa Reiti Pateko me te whakakapi ki te Hoahoa Reiti Maha Example. •I tangohia te tuhipoka i te Whakaaturanga Intel FPGA IP Design Exampte Aratohu Timata Tere e kii ana ko te putanga rorohiko a Intel Quartus Prime 21.4 e tautoko ana i te Hoahoa Tuatahi Examples. •Whakakapia te ahua o te Hanganga Whaiaronga ki te ahua tika. •Kua taapirihia he waahanga Regenerating ELF File i raro i te whakahiato me te whakamatautau i te hoahoa. •Whakahouhia te waahanga Maatauranga me nga Whakaritenga Pūmanawa hei whakauru i etahi atu taputapu whakaritenga. |
| 2021.12.13 | 21. | 20.0.0 | Tukunga tuatahi. |
Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau he kawenga, he taunahatanga ranei a Intel i puta mai i te tono, i te whakamahi ranei i nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari i whakaaehia i roto i te tuhi a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei.
*Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.
ISO 9001:2015 Kua Rehitatia
Putanga Ingarihi
Tuku Urupare
UG-20347
ID: 709308
Putanga: 2022.09.02
Tuhinga / Rauemi
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intel F-Tile DisplayPort FPGA IP Hoahoa Example [pdf] Aratohu Kaiwhakamahi F-Tile DisplayPort FPGA IP Hoahoa Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Hoahoa Example, UG-20347, 709308 |
