F-Tile JESD204C Intel FPGA IP Hoahoa Example

Mo te F-Tile JESD204C Intel® FPGA IP Design Exampte Aratohu Kaiwhakamahi

Ko tenei aratohu kaiwhakamahi e whakarato ana i nga ahuatanga, nga aratohu whakamahi, me nga korero taipitopito mo te hoahoa exampmo te F-Tile JESD204C Intel® FPGA IP e whakamahi ana i nga taputapu Intel Agilex™.

Te hunga whakarongo

Ko te tikanga tenei tuhinga mo:

• Kaihoahoa hoahoa ki te whiriwhiri IP i te wa o te waahanga whakamahere hoahoa taumata punaha
• Ko nga kaihoahoa taputapu i te wa e whakauru ana i te IP ki o raatau hoahoa taumata punaha
• Ko nga miihini whakamana i te wa o te whaihanga taumata o te punaha me te waahanga whakamana taputapu

Tuhinga e pa ana
Kei te ripanga e whai ake nei etahi atu tuhinga tohutoro e pa ana ki te F-Tile JESD204C Intel FPGA IP.

Ripanga 1. Tuhinga e Pa ana

Tohutoro	Whakaahuatanga
F-Tile JESD204C Intel FPGA IP Aratohu Kaiwhakamahi	He tuku korero mo te F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP Release Notes	Ka whakarārangihia nga huringa mo te F-Tile JESD204C F-Tile JESD204C i roto i tetahi tukunga.
Rau Raraunga Pūrere Intel Agilex	Ko tenei tuhinga e whakaatu ana i nga ahuatanga hiko, nga ahuatanga whakawhiti, nga whakaritenga whirihoranga, me te wa mo nga taputapu Intel Agilex.

Nga Acronyms me te Papakupu

Ripanga 2. Rarangi Acronym

Acronym	Whakawhanui
LEMC	Karaka Parakamaha Whakaroa Rohe
FC	Reiti karaka anga
ADC	Analog to Digital Converter
DAC	Mamati ki Analog Converter
DSP	Tukatuka Tohu Mamati
TX	Kaituku
RX	Kaiwhiwhi

Acronym	Whakawhanui
DLL	Paapapa hono raraunga
TKT	Rehita mana me te mana
CRU	Karaka me te Wae Tautuhi
ISR	Aukati i te Mahi Ratonga
FIFO	Tuatahi-Ki roto-Tuatahi-waho
SERDES	Serializer Deserializer
ECC	Hapa Whakatika Waehere
FEC	Whakatika Hapa Hapa
SERR	Takitahi Hapa (i te ECC, ka taea te whakatika)
DERR	Rapu Hapa Taurua (i te ECC, he mate)
PRBS	Pseudorandom raupapa-rua
MAC	Kaiwhakahaere Uru Media. Kei roto i te MAC te paparanga kawa, te paparanga kawe, me te paparanga hononga raraunga.
PHY	Apa tinana. Kei roto i te PHY te paparanga tinana, SERDES, taraiwa, kaiwhiwhi me te CDR.
PCS	Paparanga Waehere-a-tinana
PMA	Āpitihanga Waenga Tinana
RBD	RX Buffer Roa
UI	Wawaenga Waehe = te roanga o te moka rangatū
Tatau RBD	RX Buffer Delay te taenga mai o te huarahi hou
RBD whitiwhiti	RX Buffer Delay te whai waahi tuku
SH	Tukutahi pane
TL	Papa apa
EMIB	Piriti Hononga-maha-mate kua mau

Ripanga 3. Rarangi Papakupu

Wāhanga	Whakaahuatanga
Pūrere Kaitahuri	ADC ranei DAC converter
Pūrere arorau	FPGA ASIC ranei
Octet	He roopu moka 8, ka noho hei whakauru ki te whakawaehere 64/66 me te whakaputanga mai i te kaiwaehere.
Nibble	He huinga moka 4 ko te waahanga mahi turanga o nga whakaritenga a JESD204C
Poraka	He tohu moka-66 i hangaia e te kaupapa whakawaehere 64/66
Reiti Raina	Reeti raraunga whai hua o te hononga rangatū Reiti Raina Raina = (Mx Sx N'x 66/64 x FC) / L
Hononga Karaka	Karaka Hono = Raina Raina Raina/66.
Tāpare	He huinga octets karapīpiti e taea ai te tautuhi te tūnga o ia octet mā te tohutoro ki te tohu tīaroaro anga.
Karaka Tāpare	He karaka punaha e rere ana i te tere o te anga, me 1x me te karaka hono 2x.

Wāhanga	Whakaahuatanga
Samples mo te karaka anga	Samples mo ia karaka, te tapeke sampte karaka anga mo te taputapu kaitahuri.
LEMC	Ko te karaka o roto i whakamahia ki te whakahāngai i te rohe o te parakamaha whakaroa i waenga i nga huarahi me nga tohutoro o waho (SYSREF, Karaehe 1 ranei).
akomanga iti 0	Karekau he tautoko mo te tohenga tino. Me tuku tonu nga raraunga i runga i te huarahi ki te arai i runga i te kaikawe.
akomanga iti 1	Rooputanga whakatau ma te whakamahi i te SYSREF.
Hononga Taumaha	Hononga-a-waea me te 2 neke atu ranei nga taputapu kaitahuri.
64B / 66B Whakawaehere	Waehere raina e mahere ana i nga raraunga 64-bit ki te 66 bits hei hanga poraka. Ko te hanganga raraunga taumata turanga he poraka ka tiimata me te pane tukutahi moka-2.

Ripanga 4. Tohu

Wāhanga	Whakaahuatanga
L	Te maha o nga huarahi mo ia taputapu kaitahuri
M	Te maha o nga kaitahuri mo ia taputapu
F	Te maha o nga octets mo ia anga kei runga i te ara kotahi
S	Te maha o nga sampka tukuna mo ia kaitahuri kotahi mo ia huringa anga
N	Taumira kaitahuri
N'	Te tapeke o nga moka mo ia sample i roto i te whakatakotoranga raraunga kaiwhakamahi
CS	Te maha o nga moka whakahaere mo ia huringa sample
CF	Te maha o nga kupu whakahaere mo ia wa anga karaka mo ia hono
HD	Hōputu raraunga kaiwhakamahi Tino Nui
E	Te maha o te paraka maha i roto i te paraka maha toroa

F-Tile JESD204C Intel FPGA IP Hoahoa Exampte Aratohu Timata Tere

Ko te F-Tile JESD204C Intel FPGA IP hoahoa exampKo nga taputapu mo nga taputapu Intel Agilex e whakaatu ana i te waahi whakamatautau me te hoahoa taputapu e tautoko ana i te whakahiato me te whakamatautau taputapu.
Ka taea e koe te whakaputa i te hoahoa F-Tile JESD204C exampi roto i te putumōhio IP i roto i te rorohiko Intel Quartus® Prime Pro Edition.

Whakaahua 1. Whanaketanga Stages mo te Hoahoa Example

Hoahoa Exampte Hoahoa Poraka

Whakaatu 2. F-Tile JESD204C Hoahoa Example Hoahoa Poraka Taumata-Teitei

Ko te hoahoa exampKei roto i nga waahanga e whai ake nei:

• Pūnaha Kaihoahoa papa
  • F-Tile JESD204C Intel FPGA IP
  • JTAG ki te piriti Avalon Master
  • Kaiwhakahaere I/O (PIO) whakarara
  • Atanga Tauranga Rangatū (SPI)—kowae matua— IOPLL
  • SYSREF kaihanga
  • Example Hoahoa (ED) Mana TKT
  • Tautuhi ano i nga kaiwhakaraupapa
• Pūnaha PLL
• Kaihanga tauira
• Kaitaki tauira

Ripanga 5. Hoahoa Exampte Kōwae

Waehanga	Whakaahuatanga
Pūnaha Kaihoahoa papa	Ko te Pūnaha Kaihoahoa Papaaho e whakaatu ana i te ara raraunga F-Tile JESD204C IP me nga taputapu tautoko.
F-Tile JESD204C Intel FPGA IP	Kei roto i tenei punaha-a-roto te Kaihoahoa Platform nga IP TX me te RX F-Tile JESD204C i whakauruhia me te PHY matarua.
JTAG ki te piriti Avalon Master	Ko tenei piriti e whakarato ana i te urunga a te kaihautu papatohu punaha ki te IP kua maumaharatia i roto i te hoahoa ma te JTAG atanga.
Kaiwhakahaere I/O (PIO) whakarara	Ka whakaratohia e tenei kaiwhakahaere he atanga mahere-mahara mo sampling me te taraiwa i nga tauranga I/O.
rangatira SPI	Ka whakahaerehia e tenei kōwae te whakawhiti rangatū o nga raraunga whirihoranga ki te atanga SPI i te pito kaitahuri.
SYSREF kaihanga	Ka whakamahia e te kaihanga SYSREF te karaka hono hei karaka tohutoro me te whakaputa i nga pihini SYSREF mo te F-Tile JESD204C IP. Tuhipoka: Ko tenei hoahoa exampKa whakamahia e ia te kaihanga SYSREF ki te whakaatu i te arataki hononga hono F-Tile JESD204C IP matarua. I roto i te F-Tile JESD204C subclass 1 tono taumata punaha, me whakaputa e koe te SYSREF mai i te puna kotahi ki te karaka taputapu.
IOPLL	Ko tenei hoahoa exampKa whakamahi te IOPLL ki te whakaputa karaka kaiwhakamahi mo te tuku raraunga ki te F-Tile JESD204C IP.
ED Mana TKT	Ko tenei waahanga e whakarato ana i te mana tirotiro me te mana o SYSREF, me te whakahaere tauira whakamatautau me te mana.
Tautuhi ano i nga kaiwhakaraupapa	Ko tenei hoahoa exampE rua nga raupapa tautuhi: Tautuhi Rarangi 0—Ka hapai i te tautuhi ki te rohe roma TX/RX Avalon®, te rohe kua mapi-maharahia a Avalon, te PLL matua, te TX PHY, te TX matua, me te kaihanga SYSREF. Tautuhi Rarangi 1—Ka hapai i te tautuhi ki te RX PHY me te RX matua.
Pūnaha PLL	Te puna karaka tuatahi mo te F-tile hard IP me te whakawhiti EMIB.
Kaihanga tauira	Ka hangaia e te kaihanga tauira he PRBS r raneiamp tauira.
Kaitaki tauira	Ka tirohia e te kaitaki tauira te PRBS, r raneiamp tauira i whiwhi, ka haki he hapa ina kitea he koretake o nga raraunga sample.

Nga Whakaritenga Pūmanawa

Ka whakamahia e Intel te rorohiko e whai ake nei hei whakamatautau i te hoahoa o muaampi roto i te punaha Linux:

• Pūmanawa Intel Quartus Prime Pro Edition
• Questa*/ModelSim* or VCS*/VCS MX simulator

Te whakaputa i te Hoahoa

Hei whakaputa i te hoahoa exampmai i te ētita tawhā IP:

1. Waihangahia he kaupapa e aro ana ki te whanau taputapu Intel Agilex F-tile ka tohua te taputapu e hiahiatia ana.
2. I roto i te IP Catalog, Utauta ➤ IP Catalog, tohua F-Tile JESD204C Intel FPGA IP.
3. Tauwhāitihia he ingoa taumata-runga me te kōpaki mo to rereketanga IP ritenga. Pāwhiritia OK. Ka taapirihia e te ētita tawhā te .ip taumata-runga file ki te kaupapa o naianei. Mēnā ka ākina koe ki te tāpiri ā-ringa i te .ip file ki te kaupapa, pawhiria te Kaupapa ➤ Tāpiri/ Tango Files i te Kaupapa hei taapiri i te file.
4. I raro i te Exampripa Hoahoa, whakapūtā te hoahoa example tawhā rite whakaahuatia i roto i Design Exampte Tawhā.
5. Pāwhiritia Whakaputa Exampte Hoahoa.

Ka hangaia e te rorohiko nga hoahoa katoa files i roto i nga raarangi-iti. Ko enei files e hiahiatia ana ki te whakahaere whaihanga me te whakahiato.

Hoahoa Exampte Tawhā
Ko te F-Tile JESD204C Intel FPGA IP ētita tawhā kei roto te Exampripa Hoahoa mo koe ki te whakapūtā etahi tawhā i mua i te whakaputa i te hoahoa example.

Ripanga 6. Tawhā i roto i te Exampte Ripa Hoahoa

Tawhā	Kōwhiringa	Whakaahuatanga
Tohua Hoahoa	Mana Papatohu Pūnaha Karekau	Tīpakohia te mana papatohu pūnaha ki te uru ki te hoahoa exampte ara raraunga i roto i te papatohu pūnaha.
whaihanga	Kei, Weto	Tahuri mo te IP ki te whakaputa i nga mea e tika ana files mo te whakatairite i te hoahoa example.
Te whakahiato	Kei, Weto	Tahuri mo te IP ki te whakaputa i nga mea e tika ana files mo Intel Quartus Prime whakahiato me te whakaaturanga taputapu.
hōputu HDL (mo te whaihanga)	Verilog VDHL	Tīpakohia te whakatakotoranga HDL o te RTL files mo te whaihanga.
hōputu HDL (mo te whakahiato)	Verilog anake	Tīpakohia te whakatakotoranga HDL o te RTL files mo te whakahiato.

Tawhā	Kōwhiringa	Whakaahuatanga
Hanga 3- waea SPI kōwae	Kei, Weto	Hurihia kia taea ai te atanga SPI 3-waea, kaua ki te 4-waea.
Aratau Sysref	Kotahi te pere wā He wa poto	Tīpakohia mēnā kei te pirangi koe kia noho te whakahāngaitanga SYSREF ki te aratau pupuhi kotahi-mapu, ki te waatea, ki te waatea ranei, i runga i o whakaritenga hoahoa me te waatea o te waa. Matā-kotahi—Tīpakohia tēnei kōwhiringa kia taea ai te SYSREF he aratau pupuhi-kotahi. Ko te uara o te moka rehita sysref_ctrl[17] he 0. I muri i te F-Tile JESD204C IP tautuhi deasserts, hurihia te uara o te rehita sysref_ctrl[17] mai i te 0 ki te 1, ka ki te 0, mo te pupuhi SYSREF kotahi te pere. Waa-waa— He 50:50 te huringa mahi a SYSREF i roto i te aratau. Ko te wa SYSREF ko E*SYSREF_MULP. Awa-waahi—He huringa mahi ka taea e te SYSREF te maramatanga o te huringa karaka hono kotahi. Ko te wa SYSREF ko E*SYSREF_MULP. Mo te tautuhinga huringa mahi i waho o te awhe, ko te poraka whakatipuranga SYSREF me whakatau aunoa i te huringa mahi 1:50. Tirohia te SYSREF Kaihanga mo etahi atu korero mo te SYSREF wā.
Tīpakohia te papa	Karekau	Tīpakohia te papa mo te hoahoa example. Karekau—Ka whakakorehia e tenei whiringa nga waahanga taputapu mo te hoahoa o muaample. Ka tautuhia nga taumahi titi katoa ki nga titi mariko.
Tauira Whakamatau	PRBS-7 PRBS-9 PRBS-15 PRBS-23 Ramp	Tīpakohia te kaihanga tauira me te tauira whakamatautau kaitaki. Tauira Kaihanga—JESD204C tautoko PRBS tauira kaihanga ia raraunga sample. Ko te tikanga ko te whanui o nga raraunga ko te waahanga N+CS. He pai te hanga tauira PRBS me te kaitaki mo te hanga raraungaampte whakaongaonga mo te whakamatautau me te kore e hototahi ki te aratau whakamatautau PRBS i runga i te kaitahuri ADC/DAC. Ramp Kaihanga Tauira—JESD204C paparanga hono e mahi ana engari ka monokia te kawe i muri mai, ka warewarehia te whakauru mai i te kaiwhakaahua. Ka tukuna e ia ara he awa octet rite tonu ka piki mai i te 0x00 ki te 0xFF ka hoki ano. Ramp Ka taea te whakamatautau tauira ma te pbs_test_ctl. Kaitaki Tauira PRBS—JESD204C PRBS scrambler kei te tukutahi i a ia ano, a ko te tumanako ka taea e te matua IP te wetewete hono ki runga, kua tukutahia te kakano scrambling. Ko te kakano kakano kakano a PRBS ka eke ki te 8 octets ki te arataki whaiaro. Ramp Kaitaki Tauira—Ko te JESD204C ko te rapa kei te tukutahi me te whakaaro ka taea e te matua IP te wetewete hononga hono, kua tukutahia te kakano scrambling. Ko te octet whaimana tuatahi ka utaina hei ramp uara tuatahi. Ko nga raraunga o muri mai me piki ake ki te 0xFF ka huri ki te 0x00. Ramp Me titiro te kaitaki tauira mo te tauira rite puta noa i nga huarahi katoa.
Whakahohehia te hurihanga rangatū o roto	Kei, Weto	Tīpakohia te hurihanga rangatū o roto.
Whakahohe Hongere Tono	Kei, Weto	Tīpakohia te tauira hongere whakahau.

Hanganga Whaiaronga
Ko te hoahoa F-Tile JESD204C exampte whaiaronga kei roto i hangaia files mo te hoahoa examples.

Whakaahua 3. Hanganga Whaiaronga mo F-Tile JESD204C Intel Agilex Design Example

Ripanga 7. Whaiaronga Files

Kōpaki	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
whaihanga/tautaki	modelsim_sim.tcl tb_top_waveform.do
whaihanga/synopsys	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Whakataurite i te Hoahoa Exampte Testbench

Ko te hoahoa exampKa whakatauirahia e te testbench to hoahoa hanga.

Whakaatu 4. Tikanga

Hei whakatauira i te hoahoa, mahia nga mahi e whai ake nei:

1. Hurihia te whaiaronga mahi kiample_design_directory>/ whaihanga/ .
2. I roto i te rarangi whakahau, whakahaere i te tuhinga whaihanga. Ko te ripanga i raro nei e whakaatu ana i nga whakahau hei whakahaere i nga simulators tautoko.

Simulator	Whakahau
Questa/ModelSim	vsim -do modelsim_sim.tcl
	vsim -c -do modelsim_sim.tcl (kaore he Questa/ ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

Ka mutu te whaihanga ki nga karere e tohu ana i angitu te oma, kaore ranei.

Whakaahua 5. Whakatau Angitu
Ko tenei ahua e whakaatu ana i te karere whaihanga angitu mo te VCS simulator.

Te whakahiato i te Hoahoa Example

Hei whakahiato i te whakahiato-anake exampte kaupapa, whai i enei mahi:

1. Me whakarite hoahoa whakahiato exampkua oti te reanga.
2. I roto i te rorohiko Intel Quartus Prime Pro Edition, whakatuwheratia te kaupapa Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. I te tahua Tukatuka, pawhiria te Tīmata Whakahiato.

Whakaahuatanga Taipitopito mo te F-Tile JESD204C Design Example

Ko te hoahoa F-Tile JESD204C exampKa whakaatu a le i te mahi o te rerenga raraunga ma te whakamahi i te aratau loopback.
Ka taea e koe te tautuhi i nga tautuhinga tawhā e pai ana koe me te whakaputa i te hoahoa example.
Ko te hoahoa exampKei te waatea noa te le i roto i te aratau taarua mo nga momo rereke e rua me te Base me te PHY. Ka taea e koe te kowhiri i te Paapapa anake, i te PHY anake ranei engari ma te IP e whakaputa te hoahoa o muaample mo te Base me te PHY.

Tuhipoka:  Ko etahi whirihoranga reeti raraunga teitei ka rahua te waa. Hei karo i te korenga o te wa, whakaarohia te whakarite i te uara whakarea karaka anga iti (FCLK_MULP) ki te ripa Whirihoranga o te F-Tile JESD204C Intel FPGA IP ētita tawhā.

Waenga Pūnaha

Ko te hoahoa F-Tile JESD204C exampKa whakarato a le i tetahi rerenga whakahaere-a-rorohiko e whakamahi ana i te waeine mana pakeke me te kore tautoko papatohu punaha ranei.

Ko te hoahoa exampKa taea e te hono te hono aunoa i roto i nga aratau whakamuri o roto me waho.

JTAG ki Avalon Master Bridge
Ko te JTAG ki te Avalon Master Bridge he hononga i waenga i te punaha kaihautu kia uru atu ki te F-Tile JESD204C IP kua mapi-maharatia me te mana IP peripheral me nga rehita mana ma te JTAG atanga.

Whakaahua 6. Pūnaha me te JTAG ki Avalon Master Bridge Core

Tuhipoka:  Ko te karaka punaha me 2X tere ake i te JTAG karaka. Ko te karaka punaha he mgmt_clk (100MHz) i tenei hoahoa example.

Whakarara I/O (PIO) Core
Ko te matua whakauru/putanga (PIO) whakarara me te atanga Avalon e whakarato ana i te atanga mapi-mahara i waenga i te tauranga pononga a Avalon me te tauranga I/O. Ka hono nga tauranga I/O ki te arorau kaiwhakamahi maramara, ki nga titi I/O ranei e hono ana ki nga taputapu o waho ki te FPGA.

Whakaahua 7. PIO Core me nga Tauranga Whakauru, Tauranga Huaputa, me te Tautoko IRQ
Ma te taunoa, ka monohia e te Waahanga Kaihoahoa te Raina Ratonga Haukoti (IRQ).

Ko nga tauranga PIO I/O kua tohua ki te taumata teitei o te HDL file (io_ mana mo nga tauranga whakauru, io_ mana mo nga tauranga whakaputa).

Ko te ripanga i raro nei e whakaatu ana i te hononga tohu mo te mana me te whakahaere i nga tauranga I/O ki te whakahuri DIP me te LED i runga i te kete whanaketanga.

Ripanga 8. PIO Core I/O Tauranga

Tauranga	Bit	Waitohu
Tauranga_waho	0	USER_LED SPI hōtaka kua oti
	31:1	Kua rahuitia
I_tauranga	0	USER_DIP whakahuri rangatū o roto ka taea te Weto = 1 Kei = 0
	1	USER_DIP FPGA-hangaia SYSREF whakahohe Weto = 1 Kei = 0
	31:2	Kua rahuitia.

Kaiwhakaako SPI
Ko te waahanga matua SPI he waahanga Kaihoahoa Paerewa paerewa i roto i te whare pukapuka paerewa IP Catalog. Ka whakamahia e tenei kōwae te kawa SPI hei whakahaere i te whirihoranga o nga kaitahuri o waho (mo te example, ADC, DAC, me nga kaihanga karaka o waho) na roto i te waahi rehita kua hangaia i roto i enei taputapu.

Kei te rangatira SPI tetahi atanga mapi mahara-mahere Avalon e hono ana ki te ariki Avalon (JTAG ki te piriti matua o Avalon) ma te hononga hono-maamahara-a-Avalon. Ka whiwhi te rangatira SPI i nga tohutohu whirihoranga mai i te rangatira Avalon.

Ko te kōwae matua SPI e whakahaere ana ki te 32 nga pononga SPI motuhake. Kua whirihorahia te reiti baud SCLK ki te 20 MHz (wehea e 5).
Kua whirihorahia tenei kōwae ki te 4-waea, 24-bit atanga whanui. Mena ka tohua te kowhiringa Hangaia 3-Waea SPI Module, ka tukuna he waahanga taapiri hei huri i te putanga 4-waea o te rangatira SPI ki te waea-3.

IOPLL
Ka hangaia e te IOPLL te karaka e hiahiatia ana hei whakaputa i te frame_clk me te link_clk. Ka taea te whirihora te karaka tohutoro ki te PLL engari he iti ki te reiti raraunga/tauwehe o te 33.

• Mo te hoahoa exampe tautoko ana i te tere raraunga o 24.33024 Gbps, ko te reiti karaka mo te frame_clk me te link_clk ko 368.64 MHz.
• Mo te hoahoa exampe tautoko ana i te tere raraunga o 32 Gbps, ko te reiti karaka mo te frame_clk me te link_clk ko 484.848 MHz.

SYSREF Kaihanga
Ko te SYSREF he tohu wa tino nui mo nga kaitahuri raraunga me te atanga F-Tile JESD204C.

Ko te kaihanga SYSREF i roto i te hoahoa exampKa whakamahia te mo te kaupapa whakaatu arawhiti hononga IP matarua JESD204C IP anake. I roto i te tono taumata punaha JESD204C subclass 1, me whakaputa e koe te SYSREF mai i te puna rite ki te karaka taputapu.

Mo te F-Tile JESD204C IP, ko te SYSREF multiplier (SYSREF_MULP) o te rehita mana SYSREF e tautuhi ana i te wa SYSREF, he n-tauoti maha o te tawhā E.

Me whakarite E*SYSREF_MULP ≤16. Mo te exampe, ki te E=1, me noho te tautuhinga ture mo SYSREF_MULP i roto i te 1–16, a, ki te E=3, me noho te tautuhinga ture mo SYSREF_MULP i roto i te 1–5.

Tuhipoka:  Mena ka tautuhia e koe he SYSREF_MULP kei waho, ka whakatikahia e te kaihanga SYSREF te tautuhinga ki SYSREF_MULP=1.
Ka taea e koe te kowhiri mena kei te pirangi koe kia noho te momo SYSREF he putere-kotahi, he waahi, he waahi waatea ranei ma te Exampte ripa Hoahoa i roto i te F-Tile JESD204C Intel FPGA IP ētita tawhā.

Ripanga 9. Exampnga waahanga o te Kaitatau SYSREF Periodic and Gapped Periodic

E	SYSREF_MULP	WAA SYSREF (E*SYSREF_MULP* 32)	Huringa Mahi	Whakaahuatanga
1	1	32	1..31 (Ka taea te whakarite)	Waa-waahi
1	1	32	16 (Whakatika)	wā
1	2	64	1..63 (Ka taea te whakarite)	Waa-waahi
1	2	64	32 (Whakatika)	wā
1	16	512	1..511 (Ka taea te whakarite)	Waa-waahi
1	16	512	256 (Whakatika)	wā
2	3	19	1..191 (Ka taea te whakarite)	Waa-waahi
2	3	192	96 (Whakatika)	wā
2	8	512	1..511 (Ka taea te whakarite)	Waa-waahi
2	8	512	256 (Whakatika)	wā
2	9 (He ture kore)	64	32 (Whakatika)	Waa-waahi
2	9 (He ture kore)	64	32 (Whakatika)	wā

 

Ripanga 10. SYSREF Mana Whakahaere
Ka taea e koe te whirihora ano i nga rehita mana SYSREF mena he rereke te whakatakotoranga rehita ki te tautuhinga i tohua e koe i te wa i hangaia e koe te hoahoa o mua.ample. Whirihorahia nga rehita SYSREF i mua i te whakakorenga o te F-Tile JESD204C Intel FPGA IP i te tautuhi. Mena ka tohua e koe te kaiwhakaputa SYSREF o waho ma te
sysref_ctrl[7] rehita moka, ka taea e koe te wareware i nga tautuhinga mo te momo SYSREF, te whakarea, te huringa mahi me te wahanga.

Paraka	Uara Taunoa	Whakaahuatanga
sysref_ctrl[1:0]	2'b00: Kotahi te pere 2'b01: wā 2'b10: He waatea te wa	Momo SYSREF. Ko te uara taunoa kei runga i te tautuhinga aratau SYSREF i te Example Hoahoa ripa i roto i te F-Tile JESD204C Intel FPGA IP ētita tawhā.
sysref_ctrl[6:2]	5'b00001	SYSREF whakarea. Ko tenei mara SYSREF_MULP e tika ana ki te momo SYSREF o te waa-waa-waa. Me whirihora e koe te uara whakarea ki te whakarite ko te uara E*SYSREF_MULP kei waenganui i te 1 ki te 16 i mua i te korenga o te F-Tile JESD204C IP i te tautuhi. Mena kei waho te uara E*SYSREF_MULP i tenei awhe, ka taunoa te uara whakarea ki te 5'b00001.
sysref_ctrl[7]	Arararaunga matarua: 1'b1 Simplex TX, RX ararau ranei: 1'b0	SYSREF tīpako. Ko te uara taunoa kei runga i te tautuhinga ara raraunga i te Exampte ripa Hoahoa i roto i te F-Tile JESD204C Intel FPGA IP ētita tawhā. 0: Simplex TX, RX ranei (SYSREF waho) 1: Matarua (SYSREF o roto)
sysref_ctrl[16:8]	9'h0	Ko te huringa mahi a SYSREF i te wa e waatea ana te momo SYSREF, e waatea ana ranei. Me whirihora e koe te huringa mahi i mua i te korenga o te F-Tile JESD204C IP i te tautuhi. Uara teitei = (E*SYSREF_MULP*32)-1 Mo te example: 50% huringa mahi = (E*SYSREF_MULP*32)/2 Ka taunoa te huringa mahi ki te 50% ki te kore koe e whirihora i tenei mara rehita, mena ka whirihorahia e koe te mara rehita ki te 0 neke atu ranei i te uara morahi e whakaaetia ana.
sysref_ctrl[17]	1'b0	Te whakahaere a-ringa ina he mapere kotahi te momo SYSREF. Tuhia te 1 hei tautuhi i te tohu SYSREF ki te teitei. Tuhia te 0 hei tautuhi i te tohu SYSREF ki te iti. Me tuhi koe i te 1 me te 0 hei hanga i te putere SYSREF i te aratau mapere kotahi.
sysref_ctrl[31:18]	22'h0	Kua rahuitia.

Tautuhi Tautuhi Whakaraupapa
Ko tenei hoahoa exampe rua nga raupapa tautuhi:

• Tautuhi Rarangi 0—Ka whakahaere i te tautuhi ki te rohe roma TX/RX Avalon, te rohe kua mapi-mahara ki Avalon, te PLL matua, te TX PHY, te TX matua, me te kaihanga SYSREF.
• Tautuhi Rarangi 1—Ka hapai i te tautuhi ki te RX PHY me te RX Core.

3-Waea SPI
Ko tenei kōwae he kōwhiringa hei huri i te atanga SPI ki te waea 3.

Pūnaha PLL
E toru nga punaha PLL o runga-papa. Ko enei PLL punaha te puna karaka tuatahi mo te IP pakeke (MAC, PCS, me te FEC) me te whakawhiti EMIB. Ko te tikanga, ka whakamahi koe i te aratau karaka PLL punaha, kaore nga poraka e karaka e te karaka PMA, kaore hoki e whakawhirinaki ki te karaka ka puta mai i te FPGA matua. Ko ia punaha PLL anake e whakaputa te karaka e hono ana ki te atanga auau kotahi. Mo te exampNa, me rua nga punaha PLL hei whakahaere i tetahi atanga ki te 1 GHz me tetahi atanga ki te 500 MHz. Ma te whakamahi i te punaha PLL ka taea e koe te whakamahi takitahi i nga huarahi katoa kaore he huringa karaka karaka e pa ana ki tetahi huarahi tata.
Ka taea e ia PLL te whakamahi tetahi o nga karaka tohutoro FGT e waru. Ka taea e nga PLL Pūnaha te tiri i tetahi karaka tohutoro, he rereke ranei nga karaka tohutoro. Ka taea e ia atanga te whiriwhiri ko tehea punaha PLL ka whakamahia e ia, engari, ka kowhiria, ka whakatauhia, kaore e taea te whirihora ma te whakamahi i te whirihora hihiko.

Nga korero e pa ana
F-tile Architecture me te PMA me te FEC Direct PHY IP Aratohu Kaiwhakamahi

He korero ano mo te punaha karaka PLL i nga taputapu Intel Agilex F-tile.

Kaihanga Tauira me te Kaitaki
He pai te kaihanga tauira me te kaitaki mo te hanga s raraungaampte tirotiro me te aro turuki mo nga kaupapa whakamatautau.
Ripanga 11. Tautoko Kaihanga Tauira

Kaihanga Tauira	Whakaahuatanga
PRBS tauira kaihanga	Ko te hoahoa F-Tile JESD204C exampKo te kaihanga tauira PRBS e tautoko ana i nga tohu e whai ake nei: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp kaihanga tauira	Ko te ramp te pikinga uara tauira ma te 1 mo ia s ka whai akeample me te whanui generator o N, ka huri ki runga ki te 0 ina nga moka katoa kei roto i te samphe 1 te. Whakahohehia te ramp kaihanga tauira ma te tuhi i te 1 ki te bit 2 o te rehita tst_ctl o te poraka mana ED.
Te hongere whakahau ramp kaihanga tauira	Ko te hoahoa F-Tile JESD204C exampKa tautoko te hongere whakahau ramp kaihanga tauira mo ia ara. Ko te ramp te pikinga uara tauira ma te 1 mo te 6 moka o nga kupu whakahau. Ko te kakano timata he tauira pikinga puta noa i nga huarahi katoa.

Ripanga 12. Tautoko Kaitaki Tauira

Kaitaki Tauira	Whakaahuatanga
Kaitaki tauira PRBS	Ko te kakano kakano i roto i te kaitaki tauira ka tukutahi i a ia ano ina tutuki te F-Tile JESD204C IP i te tirohanga o te papamahi. Ko te kaitaki tauira me 8 octets mo te kakano scrambling ki te tukutahi-whaiaro.
Ramp kaitaki tauira	Ko nga raraunga whaimana tuatahi sample mo ia kaitahuri (M) ka utaina hei uara tuatahi o te ramp tauira. Raraunga muri sampKo nga uara iti me piki ake ma te 1 i ia huringa karaka ki runga ki te morahi ka huri ki te 0.

Kaitaki Tauira	Whakaahuatanga
	Mo te example, ina S=1, N=16 me WIDTH_MULP = 2, ko te whanui raraunga mo ia kaitahuri ko S * WIDTH_MULP * N = 32. Ko te nui o nga raraunga sampKo te uara he 0xFFFF. Ko te ramp Ka tirohia e te kaitaki tauira he rite nga tauira ka whakawhiwhia ki nga kaitahuri katoa.
Te hongere whakahau ramp kaitaki tauira	Ko te hoahoa F-Tile JESD204C exampKa tautoko te hongere whakahau ramp kaitaki tauira. Ko te kupu whakahau tuatahi (6 moka) kua riro ka utaina hei uara tuatahi. Ko nga kupu whakahau o muri mai i te ara kotahi me piki ake ki te 0x3F ka huri ki te 0x00. Ko te hongere whakahau ramp nga arowhai tauira mo te ramp tauira puta noa i nga huarahi katoa.

F-Tile JESD204C TX me RX IP
Ko tenei hoahoa exampKa taea e koe te whirihora i ia TX/RX i roto i te aratau ngawari, aratau taarua ranei.
Ko nga whirihoranga matarua ka taea te whakaatu mahi IP ma te whakamahi i te hurihanga rangatū o roto, o waho ranei. Ko nga TKT kei roto i te IP kaore i te arotauhia kia taea ai te mana IP me te tirotiro mana.

F-Tile JESD204C Hoahoa Exampte Karaka me te Tautuhi

Ko te hoahoa F-Tile JESD204C exampHe huinga karaka me nga tohu tautuhi.

Ripanga 13.Hoahoa Exampte Karaka

Tohu Karaka	Te aronga	Whakaahuatanga
mgmt_clk	Whakauru	Karaka rereke LVDS me te auau o 100 MHz.
refclk_xcvr	Whakauru	Karaka tohutoro whakawhiti me te auau o te reeti raraunga/tauwehe 33.
refclk_core	Whakauru	Karaka tohutoro matua me te auau rite refclk_xcvr.
in_sysref	Whakauru	tohu SYSREF. Ko te auau SYSREF teitei ko te reeti raraunga/(66x32xE).
sysref_out	Putanga
txlink_clk rxlink_clk	Roto	Karaka hono TX me RX me te auau o te reeti raraunga/66.
txframe_clk rxframe_clk	Roto	Karaka anga TX me RX me te auau o te reeti raraunga/33 (FCLK_MULP=2) Karaka anga TX me RX me te auau o te reeti raraunga/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Roto	Karaka wahanga TX me RX me te auau o te reeti raraunga/66 (FCLK_MULP=2) He teitei tonu te karaka wahanga TX me RX (1'b1) ina FCLK_MULP=1
spi_SCLK	Putanga	SPI karaka reiti baud me te auau o 20 MHz.

Ina utaina e koe te hoahoa exampki roto i tetahi taputapu FPGA, he huihuinga ninit_done o roto ka whakarite kia pai te JTAG ki te piriti Avalon Master kei te tautuhi ano me era atu poraka katoa.

Kei te kaihanga SYSREF tana tautuhi motuhake ki te wero i te hononga tukutahi mo nga karaka txlink_clk me rxlink_clk. He whanui ake tenei tikanga ki te whai i te tohu SYSREF mai i te maramara karaka o waho.

Ripanga 14. Hoahoa Example Tautuhi

Tautuhi Waitohu	Te aronga	Whakaahuatanga
ao_tuatahi	Whakauru	Patene pana te tautuhi-ao mo nga poraka katoa, haunga te JTAG ki te piriti Avalon Master.
ninit_mahi	Roto	Putanga mai i te Tautuhi Tautuhi Tuku IP mo te JTAG ki te piriti Avalon Master.
edctl_rst_n	Roto	Ko te paraka Mana ED kua tautuhia e JTAG ki te piriti Avalon Master. Ko nga tauranga hw_rst me te ao_rst_n e kore e tautuhi i te paraka Mana ED.
hw_tuatahi	Roto	Whakaoti me te whakakore i te hw_rst ma te tuhi ki te rehita rst_ctl o te poraka Mana ED. ka kii a mgmt_rst_in_n i te wa e whakahuahia ana te hw_rst.
mgmt_mua_i_n	Roto	Tautuhi ano mo nga atanga kua mapi-maharahia e Avalon o nga momo IP me nga whakaurunga o nga raupapa tautuhi:  j20c_reconfig_reset mo F-Tile JESD204C IP matarua PHY Maori spi_rst_n mo te rangatira SPI pio_rst_n mo te mana PIO me te mana whakahaere reset_in0 tauranga o te tautuhi raupapa 0 me te 1 Ko te tauranga global_rst_n, hw_rst, or edctl_rst_n ranei e kii ana ki te tautuhi i runga i te mgmt_rst_in_n.
sysref_rst_n	Roto	Tautuhi mo te poraka kaihanga SYSREF i te poraka Mana ED ma te whakamahi i te raupapa tautuhi 0 reset_out2 tauranga. Ko te raupapa tautuhi 0 reset_out2 port ka whakakore i te tautuhi mena ka maukati te PLL matua.
matua_pll_mua	Roto	Ka tautuhi ano i te PLL matua ma te raupapa tautuhi 0 reset_out0 tauranga. Ka tautuhia ano te PLL matua ka whakatauhia te tautuhi mgmt_rst_in_n.
j204c_tx_avs_rst_n	Roto	Ka tautuhi ano i te F-Tile JESD204C TX Avalon atanga mapi-mahara ma roto i te raupapa tautuhi 0. Ko te TX Avalon mahara-mahere atanga e kii ana i te wa e kii ana te mgmt_rst_in_n.
j204c_rx_avs_rst_n	Roto	Ka tautuhi ano i te F-Tile JESD204C TX Avalon atanga mapi-mahara ma roto i te raupapa tautuhi 1. Ko te RX Avalon te atanga mahara-mahere e kii ana i te wa e kii ana te mgmt_rst_in_n.
j204c_tx_rst_n	Roto	Ka tautuhi ano i te hononga F-Tile JESD204C TX me te kawe paparanga i txlink_clk, me txframe_clk, rohe. Ko te raupapa tautuhi 0 reset_out5 tauranga tautuhi i te j204c_tx_rst_n. Ka mutu tenei tautuhi mena ka maukati te PLL matua, ka whakatauhia nga tohu tx_pma_ready me tx_ready.
j204c_rx_rst_n	Roto	Ka tautuhi ano i te hononga F-Tile JESD204C RX me te kawe paparanga ki roto, rxlink_clk, rxframe_clk rohe.

Tautuhi Waitohu	Te aronga	Whakaahuatanga
		Ko te raupapa tautuhi 1 reset_out4 tauranga tautuhi ano i te j204c_rx_rst_n. Ka mutu tenei tautuhi mena ka maukati te PLL matua, ka whakatauhia nga tohu rx_pma_ready me rx_ready.
j204c_tx_rst_ack_n	Roto	Tautuhi ano i nga tohu ruru ringa ki te j204c_tx_rst_n.
j204c_rx_rst_ack_n	Roto	Tautuhi ano i nga tohu ruru ringa ki te j204c_rx_rst_n.

Whakaahua 8. Hoahoa Wā mo te Hoahoa Example Tautuhi

F-Tile JESD204C Hoahoa Exampnga Tohu

Ripanga 15. Nga Tohu Atanga Pūnaha

Waitohu	Te aronga	Whakaahuatanga
Karaka me te Tautuhi
mgmt_clk	Whakauru	100 MHz karaka mo te whakahaere punaha.
refclk_xcvr	Whakauru	Karaka tohutoro mo te F-tile UX QUAD me te PLL Pūnaha. He rite ki te reiti raraunga/tauwehe o te 33.
refclk_core	Whakauru	Karaka tohutoro PLL matua. Ka hoatu te auau karaka rite ki te refclk_xcvr.
in_sysref	Whakauru	Ko te tohu SYSREF mai i te kaihanga SYSREF o waho mo te whakatinanatanga o JESD204C Subclass 1.
sysref_out	Putanga	Ko te tohu SYSREF mo te whakatinanatanga JESD204C Subclass 1 i hangaia e te taputapu FPGA mo te hoahoa o muaampte kaupapa arawhiti hono anake.

 

Waitohu	Te aronga	Whakaahuatanga
SPI
spi_SS_n[2:0]	Putanga	Hohe iti, SPI pononga tohu tohu.
spi_SCLK	Putanga	Karaka rangatū SPI.
spi_sdio	Whakauru/Putanga	Nga raraunga whakaputa mai i te rangatira ki te pononga o waho. Whakauruhia nga raraunga mai i te pononga o waho ki te rangatira.

Waitohu	Te aronga	Whakaahuatanga
Tuhipoka:Ina whakahohea te kōwhiringa Kōwae SPI 3-Waea.
spi_MISO Tuhipoka: I te wa e kore e whakahohea te kōwhiringa Kōwae SPI 3-Waea.	Whakauru	Whakauruhia nga raraunga mai i te pononga o waho ki te rangatira SPI.
spi_MOSI Tuhipoka: I te wa e kore e whakahohea te kōwhiringa Kōwae SPI 3-Waea.	Putanga	Nga raraunga whakaputa mai i te rangatira SPI ki te taurekareka o waho.

 

Waitohu	Te aronga	Whakaahuatanga
ADC / DAC
tx_raraunga_rangatū[LINK*L-1:0]	Putanga	Raraunga putanga rangatū tere rereke ki te DAC. Kua mau te karaka ki te awa raraunga rangatū.
tx_raraunga_rangatū_n[LINK*L-1:0]
rx_raraunga_rangatū[LINK*L-1:0]	Whakauru	Raraunga whakaurunga rangatū tere rereke mai i te ADC. Kua ora ake te karaka mai i te awa raraunga rangatū.
rx_raraunga_rangatū_n[LINK*L-1:0]

 

Waitohu	Te aronga	Whakaahuatanga
Kaupapa Whānui I/O
Kaiwhakamahi_arata[3:0]	Putanga	Ka tohu i te mana mo nga tikanga e whai ake nei: [0]: Kua oti te kaupapa SPI [1]: Hapa hono TX [2]: Hapa hono RX [3]: Hapa kaitaki tauira mo nga raraunga rere Avalon
ruku_kaiwhakamahi[3:0]	Whakauru	Ko te aratau kaiwhakamahi whakauru DIP whakawhiti: [0]: Ka taea te whakaahuru rangatū o roto [1]: FPGA-hanga SYSREF whakahohea [3:2]: Kua rahuitia

 

Waitohu	Te aronga	Whakaahuatanga
I waho-o-ropu (OOB) me te Tūnga
rx_patchk_data_error[LINK-1:0]	Putanga	Ka whakatauhia tenei tohu, ka tohu kua kitea e te kaitaki tauira he hapa.
rx_link_error[LINK-1:0]	Putanga	Ka whakatauhia tenei tohu, e tohu ana ko JESD204C RX IP i kii te aukati.
tx_link_error[LINK-1:0]	Putanga	Ka whakatauhia tenei tohu, ka tohu ko JESD204C TX IP i kii te haukoti.
emb_lock_out	Putanga	Ka whakatauhia tenei tohu, ka tohu kua tutuki a JESD204C RX IP i te raka EMB.
sh_lock_out	Putanga	Ka whakatauhia tenei tohu, e tohu ana kei te maukati te pane tukutahi a JESD204C RX IP.

 

Waitohu	Te aronga	Whakaahuatanga
Avalon Streaming
rx_avst_valid[LINK-1:0]	Whakauru	Ka tohu mena ko te kaitahuri samphe tika, he muhu ranei nga raraunga ki te paparanga tono. 0: He muhu nga raraunga 1: He tika nga raraunga
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Whakauru	Kaihuri sample raraunga ki te paparanga tono.

F-Tile JESD204C Hoahoa Example Rehita Mana

Ko te hoahoa F-Tile JESD204C exampKo nga rehita i roto i te poraka Mana ED e whakamahi ana i nga korero-paita (32 bits).

Ripanga 16. Hoahoa Example Mahere Wāhitau
Kei te rohe mgmt_clk enei rehita poraka Mana ED 32-bit.

Waehanga	Wāhitau
F-Tapa JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tapa JESD204C RX IP	0x000D_0000 – 0x000D_03FF
Mana SPI	0x0102_0000 – 0x0102_001F
PIO Mana	0x0102_0020 – 0x0102_002F
Tūnga PIO	0x0102_0040 – 0x0102_004F
Tautuhi Whakaraupapa 0	0x0102_0100 – 0x0102_01FF
Tautuhi Whakaraupapa 1	0x0102_0200 – 0x0102_02FF
Mana ED	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Ripanga 17. Rēhita Momo Uru me te Whakamaramatanga
Ko tenei ripanga e whakaatu ana i te momo uru rehita mo nga IP FPGA Intel.

Momo Uru	Whakamaramatanga
RO/V	Pūmanawa panui-anake (kaore he paanga ki te tuhi). He rereke pea te uara.
RW	Ka panuihia, ka whakahokia mai e te rorohiko te uara moka o naianei. Ka tuhi me te tautuhi i te moka ki te uara e hiahiatia ana.
RW1C	Ka panuihia, ka whakahokia mai e te rorohiko te uara moka o naianei. Ka tuhia e te Pūmanawa te 0 karekau he painga. Ka tuhia e te Pūmanawa te 1 ka ūkuia te moka ki te 0 mena kua tautuhia te moka ki te 1 e te taputapu. Ka tautuhia e nga taputapu te moka ki te 1. He nui ake te kaupapa matua ake i te huinga taputapu.

Ripanga 18. Mahere Wāhitau Mana ED

Whangai	Rēhita Ingoa
0x00	rst_ctl
0x04	tuatahi_sts0
haere tonu…

Whangai	Rēhita Ingoa
0x10	rst_sts_detected0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
0x8c	tst_err0

Ripanga 19. ED Mana Poraka Mana me nga Rēhita Tūnga

Paita Whangai	Rehita	Ingoa	Urunga	Tautuhi Anō	Whakaahuatanga
0x00	rst_ctl	rst_assert	RW	0x0	Tautuhi ano i te mana. [0]: Tuhia te 1 hei kii i te tautuhi. (hw_rst) Tuhia ano te 0 ki te whakakore i te tautuhi. [31:1]: Kua rahuitia.
0x04	tuatahi_sts0	tūnga_mua	RO/V	0x0	Tautuhi i te mana. [0]: Ko te mana maukati PLL matua. [31:1]: Kua rahuitia.
0x10	rst_sts_dete cted0	rst_sts_set	RW1C	0x0	SYSREF tūnga rapunga taha mo roto, waho ranei SYSREF generator. [0]: Uara o te 1 E tohu ana ka kitea he tapa pikinga SYSREF mo te mahi akomanga 1. Ka tuhi pea te pūmanawa i te 1 hei whakawātea i tēnei moka kia taea ai te rapunga mata SYSREF hou. [31:1]: Kua rahuitia.
0x40	sysref_ctl	sysref_contr ol	RW	Te arararaunga matarua Matā kotahi: 0x00080	Mana SYSREF. Tirohia Ripanga 10 i te wharangi 17 mo etahi atu korero mo te whakamahinga o tenei rehita.
				Wā:	Tuhipoka: Ko te uara tautuhi kei runga
				0x00081	te momo SYSREF me te F-Tile
				Waahi-waahi:	JESD204C IP tautuhinga tawhā ara raraunga.
				0x00082
				Raraunga TX, RX ranei
				ara
				Kotahi-kopere:
				0x00000
				Wā:
				0x00001
				Kapi-
				wā:
				0x00002
0x44	sysref_sts	sysref_statu s	RO/V	0x0	Tūnga SYSREF. Kei roto i tenei rehita te waa SYSREF hou me nga tautuhinga huringa mahi o te kaihanga SYSREF o roto. Tirohia Ripanga 9 i te wharangi 16 mo ​​te uara ture o te waa SYSREF me te huringa mahi.
haere tonu…

Paita Whangai	Rehita	Ingoa	Urunga	Tautuhi Anō	Whakaahuatanga
					[8:0]: SYSREF wā. Ina he 0xFF te uara, ko te Wā SYSREF = 255 Ina te uara ki te 0x00, ko te wa SYSREF = 256. [17:9]: SYSREF huringa mahi. [31:18]: Kua rahui.
0x80	tst_ctl	tst_mana	RW	0x0	Mana whakamatautau. Whakamahia tenei rehita kia taea ai nga tauira whakamatautau rereke mo te kaihanga tauira me te kaitaki. [1:0] = Marae kua rahuitia [2] = ramp_whakamatautau_ctl 1'b0 = Whakahohe PRBS tauira kaihanga me te kaitaki 1'b1 = Whakahohe ramp kaihanga tauira me te kaitaki [31:3]: Kua rahui.
0x8c	tst_err0	tst_hapa	RW1C	0x0	Hapa haki mo te Hononga 0. Ina he 1'b1 te moka, ka tohu kua puta he hapa. Me whakatau e koe te hapa i mua i te tuhi i te 1'b1 ki ia moka hei whakakore i te haki hapa. [0] = Hapa kaitaki tauira [1] = tx_link_error [2] = rx_link_error [3] = Hapa kaitaki tauira whakahau [31:4]: Kua rahui.

Tuhinga o mua mo te F-Tile JESD204C Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

Putanga Tuhinga	Intel Quartus Prime Putanga	Putanga IP	Huringa
2021.10.11	21.3	1.0.0	Tukunga tuatahi.

Tuhinga / Rauemi

intel F-Tile JESD204C Intel FPGA IP Hoahoa Example [pdf] Aratohu Kaiwhakamahi F-Tile JESD204C Intel FPGA IP Hoahoa Example, F-Tile JESD204C, Intel FPGA IP Hoahoa Example, IP Hoahoa Example, Hoahoa Example

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