F Tile Serial Lite IV Intel FPGA IP Aratohu Kaiwhakamahi

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F Tile Serial Lite IV Intel FPGA IP

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi
Kua whakahoutia mo Intel® Quartus® Prime Design Suite: 22.1 IP Putanga: 5.0.0

Putanga Tuihono Tuku Urupare

UG-20324

ID: 683074 Putanga: 2022.04.28

Ihirangi
Ihirangi
1. Mo te F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi…………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Neke atuview………………………………………………………. 6 2.1. Tukuna Nga korero……………………………………………………………………………………..7 2.2. Ngā Āhuatanga Tautoko…………………………………………………………………………………….. 7 2.3. Taumata Tautoko Putanga IP…………………………………………………………………………..8 2.4. Tautoko Koeke Tere Pūrere………………………………………………………………………………..8 2.5. Te Whakamahi Rauemi me te Rooputanga……………………………………………………………………9 2.6. Paitanga Aratuku……………………………………………………………………………………. 9
3. Te Haamataraa………………………………………………………………………………………………. 11 3.1. Te Tāuta me te Raihana Intel FPGA IP Core…………………………………………………… 11 3.1.1. Intel FPGA IP Aratau Aromātai………………………………………………………………. 11 3.2. Te Tautuhi i nga Tawhā IP me nga Kōwhiringa……………………………………………………………… 14 3.3. Hangaia File Hanganga………………………………………………………………………… 14 3.4. Whakatauhanga Intel FPGA IP Core………………………………………………………………………… 16 3.4.1. Te Whakatau me te Manatoko i te Hoahoa…………………………………………………… 17 3.5. Te Whakakotahi i nga Kohiko IP ki etahi atu Utauta EDA………………………………………………………. 17 3.6. Te whakahiato i te Hoahoa Katoa……………………………………………………………………………………..18
4. Whakaahuatanga Mahi…………………………………………………………………………………….. 19 4.1. Ara Raraunga TX………………………………………………………………………………………………..20 4.1.1. TX MAC Whāurutau………………………………………………………………………….. 21 4.1.2. Kōkuhu Kupu Mana (CW)…………………………………………………………………… 23 4.1.3. TX CRC……………………………………………………………………………………28 4.1.4. TX MII Encoder…………………………………………………………………………….29 4.1.5. TX PCS me PMA………………………………………………………………………….. 30 4.2. RX Raraunga…………………………………………………………………………………………. 30 4.2.1. RX PCS me PMA………………………………………………………………………….. 31 4.2.2. RX MII Pūwaehere………………………………………………………………………… 31 4.2.3. RX CRC…………………………………………………………………………………….. 31 4.2.4. RX Deskew……………………………………………………………………………………….32 4.2.5. Tango RX CW…………………………………………………………………………35 4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture…………………………………………. 36 4.4. Tautuhi Anō me te Whakataki Hononga………………………………………………………………………………..37 4.4.1. TX Tautuhianu me te Raupapa Arawhiti………………………………………………………………. 38 4.4.2. RX Tautuhi me te Raupapa Arawhiti………………………………………………………. 39 4.5. Te Reeti Hononga me te Tataitanga Whainga Aratuku……………………………………………………………….. 40
5. Tawhā…………………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Waitohu Atanga…………………………………………….. 44 6.1. Waitohu Karaka……………………………………………………………………………………………….44 6.2. Tautuhi Tautuhi Tohu……………………………………………………………………………………………… 44 6.3. Nga Tohu MAC……………………………………………………………………………………………….. 45 6.4. Waitohu Whirihora Anō Whakawhiti……………………………………………………………… 48 6.5. Nga Tohu PMA……………………………………………………………………………………………….. 49

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 2

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Ihirangi
7. Te hoahoa me te F-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Tautuhi Arahi Aratohu…………………………………………………………………………………….. 51 7.2. Nga Aratohu Whakahaere Hapa…………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP Kaiwhakamahi Aratohu Archives…………………………………………. 52 9. Tuhinga o mua Tuhinga mo te F-Tile Serial Lite IV Intel FPGA IP Aratohu Kaiwhakamahi……53

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1. Mo te F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi

Ko tenei tuhinga e whakaatu ana i nga ahuatanga IP, te whakaahuatanga hoahoanga, nga huarahi ki te whakaputa, me nga aratohu ki te hoahoa i te F-Tile Serial Lite IV Intel® FPGA IP ma te whakamahi i nga whakawhiti F-tile i roto i nga taputapu Intel AgilexTM.

Te hunga whakarongo

Ko tenei tuhinga mo nga kaiwhakamahi e whai ake nei:
· Hangaia nga kaihoahoa ki te whiriwhiri IP i te wa o te waahanga whakamahere hoahoa taumata-puna
· Kaihoahoa taputapu i te wa e whakauru ana i te IP ki roto i o raatau hoahoa taumata-na
· Nga miihini whakamana i te wa o te whaihanga o te taumata-puna me nga waahanga whakamana taputapu

Tuhinga e pa ana

Kei te ripanga e whai ake nei etahi atu tuhinga tohutoro e pa ana ki te F-Tile Serial Lite IV Intel FPGA IP.

Ripanga 1.

Tuhinga e pa ana

Tohutoro

F-Tile Serial Lite IV Intel FPGA IP Hoahoa Exampte Aratohu Kaiwhakamahi

Rau Raraunga Pūrere Intel Agilex

Whakaahuatanga
Ko tenei tuhinga e whakarato ana i te whakatipuranga, nga aratohu whakamahi, me te whakaahuatanga mahi mo te F-Tile Serial Lite IV Intel FPGA IP hoahoa exampi roto i nga taputapu Intel Agilex.
Ko tenei tuhinga e whakaatu ana i nga ahuatanga hiko, nga ahuatanga whakawhiti, nga whakaritenga whirihoranga, me te wa mo nga taputapu Intel Agilex.

Ripanga 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Nga Acronyms me te Rarangi Kupu Acronym
Acronym

Kupu Whakahaere Roha Reed-Solomon Whakamua Hapa Whakatikatika Waenga-a-tinana Apitihanga Waenga Kaituku Kaiwhiwhi Pulse-AmpLitude Whakakotahitanga 4-Kaupae Kore-hoki-ki-kore

haere tonu…

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. *Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

ISO 9001:2015 Kua Rehitatia

1. Mo te F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 683074 | 2022.04.28

PCS MII XGMII

Acronym

Roha Whakawaehere-a-tinana Waehere-a-roto Atanga Motuhake Atanga 10 Gigabit Media Atanga Motuhake

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F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 5

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2. F-Tile Serial Lite IV Intel FPGA IP Neke atuview

Whakaahua 1.

Ko te F-Tile Serial Lite IV Intel FPGA IP e pai ana mo te whakawhitiwhiti korero raraunga teitei mo te maramara-ki-marama, te poari-ki-poari, me nga tono papamuri.

Ko te F-Tile Serial Lite IV Intel FPGA IP e whakauru ana i te mana uru pāpāho (MAC), te taapiri-a-tinana (PCS), me nga poraka taapiri pāpāho tinana (PMA). Ka tautokohia e te IP nga tere whakawhiti raraunga ki runga ki te 56 Gbps mo ia ara me te nui o nga huarahi PAM4 e wha, te 28 Gbps ranei mo ia ara me te nui o nga huarahi 16 NRZ. Ka tukuna e tenei IP te bandwidth teitei, te papa iti o runga, te iti o te tatau I/O, me te tautoko i te tauineine teitei i roto i te maha o nga huarahi me te tere. He ngawari hoki tenei IP ki te whirihora ano me te tautoko i te whānuitanga o nga reiti raraunga me te aratau Ethernet PCS o te whakawhiti F-tile.

Ka tautokohia e tenei IP nga momo tuku e rua:
· Aratau Taketake–He aratau roma parakore tenei ka tukuna nga raraunga me te kore te tiimata-pakete, te hurihanga kau, me te mutunga-o-pakete hei whakanui i te bandwidth. Ka tangohia e te IP nga raraunga whaimana tuatahi hei timatanga o te pakaru.
· Aratau katoa–He aratau whakawhiti putea tenei. I tenei aratau, ka tukuna e te IP he pakaru me te huringa tukutahi i te timatanga me te mutunga o te kete hei kaiwehe.

F-Tile Serial Lite IV High Level Poraka Hoahoa

Avalon Streaming Atanga TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64*n moka ara (aratau NRZ)/ 2*n moka ara (aratau PAM4)

TX MAC

Whakauru Whakauru

MII ENCODED

PCS Ritenga

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Moka Ara (aratau PAM4)/ n Moka Ara (aratau NRZ)
TX Atanga Rangatū

Avalon Streaming Atanga RX
64*n moka ara (aratau NRZ)/ 2*n moka ara (aratau PAM4)

RX PCS

CW RMV

DESKEW

MII

& WHAKATARI WAEWAE

RX MII

EMIB

WHAKATAHI PAKARANGA TANGATA & FEC DESCRAMBLER

RX PMA

TKT

2n Nga Moka Ara (aratau PAM4)/ n Nga Moka Ara (Aratau NRZ) RX Atanga Rangatū
Avalon Memory-Mapped Interface Rēhita Whirihora

Poutohu

Te arorau ngawari

Te arorau pakeke

ISO 9001:2015 Kua Rehitatia

2. F-Tile Serial Lite IV Intel FPGA IP Neke atuview 683074 | 2022.04.28

Ka taea e koe te whakaputa F-Tile Serial Lite IV Intel FPGA IP hoahoa exampki te ako atu mo nga ahuatanga IP. Tirohia te F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi.
Nga korero e pa ana · Whakaahuatanga Mahi i te wharangi 19 · F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

2.1. Tukua nga korero

Ko nga putanga Intel FPGA IP e rite ana ki nga putanga rorohiko Intel Quartus® Prime Design Suite tae noa ki te v19.1. Ka timata i roto i te putanga rorohiko Intel Quartus Prime Design Suite 19.2, he kaupapa whakaputa hou a Intel FPGA IP.

Ka huri te tau Intel FPGA IP (XYZ) me ia putanga rorohiko Intel Quartus Prime. He huringa i roto i:

· E tohu ana te X i te whakahounga nui o te IP. Mena ka whakahouhia e koe te rorohiko Intel Quartus Prime, me whakahou e koe te IP.
· E tohu ana te IP kei roto nga ahuatanga hou. Whakahouhia to IP ki te whakauru i enei ahuatanga hou.
· Ka tohu a Z kei roto i te IP nga huringa iti. Whakahoutia to IP ki te whakauru i enei huringa.

Ripanga 3.

F-Tile Serial Lite IV Intel FPGA IP Release Information

Putanga IP Putanga Intel Quartus Prime Putanga Whakaputa Waehere Whakatau Ra

5.0.0 22.1 2022.04.28 IP-SLITE4F

Whakaahuatanga

2.2. Āhuatanga Tautoko
Kei te ripanga e whai ake nei nga ahuatanga e waatea ana i te F-Tile Serial Lite IV Intel FPGA IP:

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F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 7

2. F-Tile Serial Lite IV Intel FPGA IP Neke atuview 683074 | 2022.04.28

Ripanga 4.

F-Tile Serial Lite IV Intel FPGA IP Features

Āhuahira

Whakaahuatanga

Whakawhiti Raraunga

· Mo te aratau PAM4:
— E tautoko ana a FHT i te 56.1, 58, me te 116 Gbps mo ia ara me te nui o nga huarahi e 4.
— Ka tautoko a FGT ki te 58 Gbps mo ia ara me te 12 nga huarahi morahi.
Tirohia te Ripanga 18 i te wharangi 42 mo etahi atu korero mo nga reiti raraunga whakawhiti mo te aratau PAM4.
· Mo te aratau NRZ:
— E tautoko ana a FHT i te 28.05 me te 58 Gbps mo ia ara me te 4 ara nui.
— Kei te tautoko a FGT ki te 28.05 Gbps mo ia ara me te 16 nga huarahi morahi.
Tirohia te Ripanga 18 i te wharangi 42 mo etahi atu korero mo nga reeti raraunga whakawhiti mo te aratau NRZ.
· E tautoko ana i te rere haere tonu (Basic) me te paatete (Full) aratau.
· E tautoko ana i nga putea anga o runga iti.
· Ka tautokohia te whakawhiti paita mo nga rahi pakaru.
· Ka tautokohia e te kaiwhakamahi te tirohanga ara aunoa ranei.
· E tautoko ana i te waa whakatikatika ka taea te whakarite.

PCS

· Ka whakamahi i te arorau IP pakeke e hono ana ki nga kaiwhakawhitiwhiti Intel Agilex F-tile mo te whakahekenga rauemi arorau ngawari.
· Ka tautokohia te aratau whakarereke PAM4 mo te 100GBASE-KP4 whakaritenga. Ko te RS-FEC i nga wa katoa ka taea i tenei aratau whakarereke.
· Ka tautokohia te NRZ me te aratau whakarereke RS-FEC.
· Tautoko 64b/66b whakawaehere whakawaehere.

Te Rapu Hapa me te Whakahaere

· Ka tautokohia te tirotiro hapa CRC i runga i nga huarahi raraunga TX me RX. · Ka tautokohia te tirotiro hapa hononga RX. · E tautoko ana i te kitenga hapa RX PCS.

Atanga

· Ka tautokohia anake te whakawhiti putea taarua katoa me nga hononga motuhake.
· Ka whakamahi i te hono ira-ki-ira ki nga taputapu FPGA maha me te iti o te roanga whakawhiti.
· Ka tautoko i nga whakahau kua tautuhia e te kaiwhakamahi.

2.3. Taumata Tautoko Putanga IP

Ko te rorohiko Intel Quartus Prime me te tautoko taputapu Intel FPGA mo te F-Tile Serial Lite IV Intel FPGA IP e whai ake nei:

Ripanga 5.

Putanga IP me te Taumata Tautoko

Intel Quartus Prime 22.1

Pūrere Intel Agilex F-tile transceivers

Putanga IP Whakaakoranga Whakahiato Maama Hoahoa

5.0.0

2.4. Tautoko Tohu Tere Pūrere
Ko te F-Tile Serial Lite IV Intel FPGA IP e tautoko ana i nga tohu tere e whai ake nei mo nga taputapu Intel Agilex F-tile: · Koeke tere Transceiver: -1, -2, me -3 · Koeke tere matua: -1, -2, me - 3

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 8

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Nga korero e pa ana
Rau Raraunga Pūrere Intel Agilex Ētahi atu pārongo mo te reiti raraunga tautoko i roto i te Intel Agilex F-tile transceivers.

2.5. Te Whakamahi Rauemi me te Rooputanga

Ko nga rauemi me te roa mo te F-Tile Serial Lite IV Intel FPGA IP i riro mai i te putanga rorohiko Intel Quartus Prime Pro Edition 22.1.

Ripanga 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Whakamahi Rauemi
Ko te ine inenga kei runga i te roanga haerenga a tawhio noa mai i te whakauru matua TX ki te putanga matua RX.

Momo Whakawhiti

He rereke

Te maha o te Aratau Raraunga Raraunga RS-FEC ALM

Latency (TX matua huringa karaka)

FGT

28.05 Gbps NRZ 16

Te Hunga Taketake 21,691 65

Tino Haua 22,135 65

Basic Enabled 21,915 189

Katoa kua Whakahohea 22,452 189

58 Gbps PAM4 12

Basic Enabled 28,206 146

Katoa kua Whakahohea 30,360 146

FHT

58 Gbps NRZ

Basic Enabled 15,793 146

Katoa kua Whakahohea 16,624 146

58 Gbps PAM4 4

Basic Enabled 15,771 154

Katoa kua Whakahohea 16,611 154

116 Gbps PAM4 4

Basic Enabled 21,605 128

Katoa kua Whakahohea 23,148 128

2.6. Te Aratuku Pai

Ripanga 7.

Aratuku Putanga

Taurangi Aratau Whakawhiti

PAM4

Aratau roma RS-FEC

Whakahohea Katoa

Kaupapa Whakahohe

Reiti moka atanga rangatū i Gbps (RAW_RATE)
Rahi pakaru o te whakawhiti i te maha o te kupu (BURST_SIZE) (1)
Wā tīaroaro i roto i te huringa karaka (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Tautuhinga

NRZ

Ki tonu

Kua haua

Whakahohe

28.0

2,048

4,096

Taketake Kua Mono 28.0

Whakahohe 28.0

4,194,304

4,096

4,096 tonu…

(1) Ko te BURST_SIZE mo te aratau Taketake ka whakatata atu ki te mutunga kore, no reira he nui te whakamahi.

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F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 9

2. F-Tile Serial Lite IV Intel FPGA IP Neke atuview 683074 | 2022.04.28

Taurangi

Tautuhinga

64/66b whakawaehere

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

I runga ake i te rahi pakaru i te maha o te kupu (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Tīaroaro wā tohu 81,915 i roto i te huringa karaka (ALIGN_MARKER_PERIOD)

81,915

81,916

Tirohanga te whanui tohu ki te 5

huringa karaka

(ALIGN_MARKER_WIDTH)

Te kaha aratuku (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Reeti whai hua (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Te auau karaka kaiwhakamahi teitei (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Te Reeti Hononga Moohiohio Paatahi me te Tatautanga Maamaa Aratuku kei te wharangi 40

(2) I roto i te aratau Katoa, ko te BURST_SIZE_OVHD te rahi kei roto i nga Kupu Mana START/END takirua i roto i te awa raraunga.
(3) Mo te aratau Taketake, he 0 te BURST_SIZE_OVHD na te mea karekau he START/END i te wa e rere ana.
(4) Tirohia te Reiti Hononga me te Tatautanga Whainga Aratuku mo te tatauranga pai o te bandwidth.
(5) Tirohia te Reiti Hononga me te Tatautanga Whainga Aratuku mo te tatauranga reiti whai hua.
(6) Tirohia te Reiti Hononga me te Tatautanga Whainga Aratuku mo te tatauranga auau karaka a te kaiwhakamahi.

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 10

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3. Te Timata

3.1. Te whakauru me te Raihana Intel FPGA IP Cores

Kei roto i te whakaurunga rorohiko Intel Quartus Prime te whare pukapuka IP FPGA Intel. Ka whakaratohia e tenei whare pukapuka te maha o nga konae IP whaihua mo to mahi whakaputa me te kore e hiahiatia he raihana taapiri. Ko etahi matua Intel FPGA IP e hiahia ana ki te hoko raihana motuhake mo te mahi whakaputa. Ko te Aratau Aromātai IP Intel FPGA ka taea e koe te arotake i enei punaha Intel FPGA IP kua raihanatia i roto i te whaihanga me te taputapu, i mua i te whakatau ki te hoko raihana matua IP whakangao katoa. Me hoko noa koe i te raihana whakangao katoa mo nga matua Intel IP whai raihana i muri i to whakaoti i nga whakamatautau taputapu me te reri ki te whakamahi i te IP ki te whakaputa.

Ka whakauruhia e te rorohiko Intel Quartus Prime nga matua IP ki nga waahi e whai ake nei ma te taunoa:

Whakaahua 2.

Ara Whakauru IP Core
intelFPGA(_pro) quartus – Kei roto te Intel Quartus Prime software ip – Kei roto te Intel FPGA IP whare pukapuka me te tuatoru-rōpū IP cores altera – Kei roto te Intel FPGA IP library source code – Kei roto te puna Intel FPGA IP files

Ripanga 8.

Wāhi Tāuta IP Core

Tauwāhi

Pūmanawa

:intelFPGA_proquarttusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Pūhara Windows* Linux*

Tuhipoka:

Ko te rorohiko Intel Quartus Prime kaore i te tautoko i nga waahi i te ara whakauru.

3.1.1. Intel FPGA IP Aratau Aromātai
Ko te Aratau Aromātai IP Intel FPGA IP koreutu ka taea e koe te arotake i nga punaha IP Intel FPGA IP whai raihana i roto i te whaihanga me te taputapu i mua i te hoko. Kei te tautoko te Aratau Aromātai IP Intel FPGA i nga arotakenga e whai ake nei me te kore raihana taapiri:
· Whakatauritehia te whanonga o te Intel FPGA IP matua whai raihana i roto i to punaha. · Manatokohia te mahi, te rahi me te tere o te matua IP kia tere me te ngawari. · Hangaia he kaupapa taputapu wa-iti files mo nga hoahoa kei roto nga IP IP. · Whakatakahia he taputapu me to IP matua me te manatoko i to hoahoa i roto i nga taputapu.

ISO 9001:2015 Kua Rehitatia

3. Te Timata
683074 | 2022.04.28
Kei te tautoko te Aratau Aromātai IP Intel FPGA i nga momo mahi e whai ake nei:
· Tethered–Ka taea te whakahaere i te hoahoa kei roto te Intel FPGA IP whai raihana mo te wa roa me te hononga i waenga i to papa me te rorohiko kaihautu. Ko te aratau herea e hiahia ana he roopu mahi whakamatautau tahi (JTAG) taura hono i waenga i te JTAG tauranga i runga i to papa me te rorohiko kaihautu, kei te whakahaere i te Intel Quartus Prime Programmer mo te roanga o te wa aro mātai taputapu. He iti noa te whakaurunga o te rorohiko rorohiko Intel Quartus Prime a te Kaihōtaka, karekau he raihana Intel Quartus Prime. Ko te rorohiko kaihautu e whakahaere ana i te wa arotake ma te tuku tohu i ia wa ki te taputapu ma te JTAG tauranga. Mena ka tautokohia e nga matua IP whai raihana katoa i roto i te hoahoa te aratau herea, ka haere te wa arotake kia pau ra ano tetahi arotakenga matua IP. Mena ka tautokohia e nga matua IP katoa te wa arotakenga mutunga kore, karekau te taputapu e mutu.
· Whakakorea–Ka taea te whakahaere i te hoahoa kei roto te IP whai raihana mo te wa poto. Ka hoki te matua IP ki te aratau kore herea mena ka momotu te taputapu mai i te rorohiko kaihautu e whakahaere ana i te rorohiko Intel Quartus Prime. Ka hoki ano te matua IP ki te aratau kore here mena kaare etahi atu kaupapa IP whai raihana i roto i te hoahoa e tautoko ana i te aratau here.
Ka pau te wa arotake mo tetahi Intel FPGA IP whai raihana i roto i te hoahoa, ka mutu te mahi o te hoahoa. Ko nga matua IP katoa e whakamahi ana i te Aratau Aromātai IP Intel FPGA IP i te wa kotahi i te wa ka pau tetahi IP matua i roto i te hoahoa. Ka pau te wa aro mātai, me whakahōtaka anō e koe te taputapu FPGA i mua i te haere tonu ki te manatoko taputapu. Hei whakawhānui ake i te whakamahinga o te IP matua mo te hanga, hokona he raihana whakaputa katoa mo te matua IP.
Me hoko e koe te raihana me te whakaputa i te taviri raihana whakangao katoa i mua i to whakaputa i tetahi papatono taputapu kore here file. I roto i te Aratau Aromātai IP FPGA Intel, ka hangaia e te Kaihanga he papatono taputapu wa-iti file ( _time_limited.sof) ka pau i te tepe wa.

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Whakaahua 3.

Intel FPGA IP Rere Aratau Aromātai
Tāutahia te Intel Quartus Prime Software me te Intel FPGA IP Library

Whakaritea me te Whakahou i tetahi Intel FPGA IP Core kua Raihanatia

Manatokohia te IP i roto i te Simulator Tautokohia

Whakahiato te Hoahoa i roto i te Intel Quartus Prime Software

Hangaia he Papatonotanga Pūrere-Waiti File

Papatonohia te Pūrere Intel FPGA me te Manatoko i te Mahi i runga i te Poari
Karekau he IP kua Riri mo te Whakamahinga Whakaputa?
Ae Hoko he Whakangao Katoa
Raihana IP

Tuhipoka:

Whakauruhia he IP Raihana ki nga Hua Aromoni
Tirohia te aratohu kaiwhakamahi o ia matua IP mo nga taahiraa tawhā me nga taipitopito whakatinanatanga.
Ka whakamanahia e Intel nga konae IP mo ia nohoanga, mo ake tonu atu. Kei roto i te utu raihana te tiaki me te tautoko i te tau tuatahi. Me whakahou e koe te kirimana tiaki kia whiwhi whakahōutanga, whakatika iro, me te tautoko hangarau i tua atu i te tau tuatahi. Me hoko e koe he raihana whakangao katoa mo nga matua Intel FPGA IP e hiahia ana ki te raihana whakaputa, i mua i te whakaputa kaupapa files ka taea e koe te whakamahi mo te wa mutunga kore. I roto i te Aratau Aromātai IP FPGA Intel, ka hangaia e te Kaihanga he papatono taputapu wa-iti file ( _time_limited.sof) ka pau i te tepe wa. Ki te tiki i o taviri raihana whakangao, toro atu ki te Intel FPGA Self-Service Licensing Center.
Ko nga Whakaaetanga Raihana Pūmanawa Intel FPGA e whakahaere ana i te whakaurunga me te whakamahi i nga konae IP whai raihana, te rorohiko hoahoa Intel Quartus Prime, me nga konae IP kore raihana katoa.

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Nga korero e pa ana · Intel FPGA Raihana Tautoko Pokapū Tautoko · Whakataki ki te Intel FPGA Pūmanawa Tāuta me te Raihana
3.2. Te tautuhi i nga Tawhā IP me nga Kōwhiringa
Ko te ētita tawhā IP ka taea e koe te whirihora tere i to rereketanga IP ritenga. Whakamahia nga mahi e whai ake nei hei tautuhi i nga whiringa IP me nga tawhā i roto i te rorohiko Intel Quartus Prime Pro Edition.
1. Ki te kore koe e whai kaupapa Intel Quartus Prime Pro Edition hei whakauru i to F-Tile Serial Lite IV Intel FPGA IP, me hanga e koe tetahi. a. I roto i te Intel Quartus Prime Pro Edition, pawhiria File Ruānuku Kaupapa Hou ki te hanga kaupapa Quartus Prime hou, ranei File Tuwhera Kaupapa hei whakatuwhera i tetahi kaupapa Quartus Prime. Ka akiaki koe e te ruānuku ki te tautuhi i tetahi taputapu. b. Tauwhāitihia te whanau taputapu Intel Agilex ka kowhiria he taputapu hanga F-tile e tutuki ana i nga whakaritenga tere mo te IP. c. Pāwhiritia te Mutu.
2. I roto i te Putumōhio IP, kimihia ka tohua te F-Tile Serial Lite IV Intel FPGA IP. Ka puta te Matapihi Rerekē IP Hou.
3. Tauwhāitihia he ingoa taumata-runga mo to rereketanga IP ritenga hou. Ka tiakina e te ētita tawhā ngā tautuhinga rerekētanga IP i roto i te a file whakaingoatia .ip.
4. Pāwhiritia OK. Ka puta te ētita tawhā. 5. Tauwhāitihia ngā tawhā mō tō rerekētanga IP. Tirohia te waahanga Tawhā mo
nga korero mo te F-Tile Serial Lite IV Intel FPGA IP tawhā. 6. Ki te hiahia, ki te whakaputa i te papa whakamatautau whaihanga, te whakahiato me te hoahoa taputapu
exampte, whai i nga tohutohu i roto i te Design Exampte Aratohu Kaiwhakamahi. 7. Pāwhiritia Hanga HDL. Ka puta te pouaka korero Whakatupuranga. 8. Whakaritea te putanga file nga whiringa whakatipuranga, katahi ka paato Whakaputa. Ko te rereketanga IP
files whakaputa rite ki o koutou whakaritenga. 9. Pāwhiritia Mutu. Ka taapirihia e te ētita tawhā te .ip taumata-runga file ki te au
kaupapa aunoa. Mēnā ka ākina koe ki te tāpiri ā-ringa i te .ip file ki te kaupapa, pawhiria te Kaupapa Tāpiri/Tangohia Files i te Kaupapa hei taapiri i te file. 10. Whai muri i te whakaputa me te whakamohio i to rerekeetanga IP, mahia nga tohu tohu tika hei hono i nga tauranga me te whakarite i nga tawhā RTL e tika ana mo ia tauira.
Ngā Tawhā Mōhiohio Pānga i te whārangi 42
3.3. Hangaia File Hanganga
Ko te rorohiko Intel Quartus Prime Pro Edition ka whakaputa i te putanga IP e whai ake nei file hanganga.
Mo nga korero mo te file hanganga o te hoahoa exampe, tirohia ki te F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi.

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Whakaatu 4. F-Tile Serial Lite IV Intel FPGA IP Hangaia Files
.ip – whakauru IP file

Rerekētanga IP files

_ Rerekētanga IP files

exampte_hoahoa

.cmp – whakapuakanga wahanga VHDL file _bb.v – Verilog HDL pouaka pango EDA synthesis file _inst.v me .vhd – Sampte tauira inamata .xml- purongo XML file

Exampte waahi mo to hoahoa matua IP example files. Ko te tauwāhi taunoa he example_design, engari ka akiakihia koe ki te tautuhi i tetahi ara rereke.

.qgsimc – Ka whakarārangihia ngā tawhā whaihanga hei tautoko i te whakahoutanga āpiti .qgsynthc – Ka whakarārangihia ngā tawhā kōtuitanga hei tautoko i te whakahoutanga āpiti

.qip – Rarangi te whakahiato IP files

_generation.rpt- purongo whakatipuranga IP

.sopcinfo- Pūmanawa taputapu-mekameka whakauru file .html- Hononga me te raraunga mahere mahara

.csv – Taumahi titi file

.spd – Ka whakakotahi i nga tuhinga whaihanga takitahi

sim whaihanga files

te whakahiato IP files

.v whaihanga taumata-runga file

.v Whakakotahitanga IP taumata-runga file

Nga tuhi simulator

Nga whare pukapuka matua

synth
Te whakahiatotanga files

sim
Whakaakoranga Raro files

Ripanga 9.

F-Tile Serial Lite IV Intel FPGA IP Hangaia Files

File Ingoa

Whakaahuatanga

.ip

Ko te punaha Kaihoahoa Paerewa, he rerekeetanga IP taumata-runga ranei file. Ko te ingoa ka hoatu e koe to rerekee IP.

.cmp

Te Whakapuakanga Wae VHDL (.cmp) file he kuputuhi file kei roto nga whakamaaramatanga whanui me te tauranga ka taea e koe te whakamahi i roto i te hoahoa VHDL files.

.html

He ripoata kei roto nga korero hononga, he mapi mahara e whakaatu ana i te wahitau o ia pononga mo ia rangatira e hono ana, me nga taumahi tawhā.

_whakatupuranga.rpt

IP, Raraunga Whakatupuranga Kaihoahoa ranei file. He whakarāpopototanga o ngā karere i te wā whakangao IP.

.qgsimc

Ka whakarārangihia nga tawhā whaihanga hei tautoko i te whakatipuranga hou.

.qgsynthc

Ka whakarārangihia ngā tawhā kōtuitanga hei tautoko i te whakatipuranga āpiti.

.qip

Kei roto nga korero katoa e hiahiatia ana mo te waahanga IP hei whakauru me te whakahiato i te waahanga IP i roto i te rorohiko Intel Quartus Prime.
haere tonu…

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File Ingoa .sopcinfo
.csv .spd _bb.v _inst.v ranei _inst.vhd .regmap
.svd
.v ranei .vhd kaiakopono/ synopsys/vcs/ synopsys/vcsmx/ xcelium/ submodules/ /

Whakaahuatanga
He whakaahua i nga hononga me nga taapiri waahanga IP i to punaha Kaihoahoa Platform. Ka taea e koe te tarai i ona ihirangi ki te tiki whakaritenga ina whakawhanake koe i nga taraiwa rorohiko mo nga waahanga IP. Ko nga taputapu o raro penei i te mekameka taputapu Nios® II e whakamahi ana i tenei file. Ko te .sopcinfo file me te punaha.h file i hangaia mo te mekameka taputapu Nios II ko nga korero mahere wahitau mo ia pononga e pa ana ki ia rangatira e uru ana ki te taurekareka. He mapi wahitau rereke pea nga rangatira rereke hei uru ki tetahi waahanga taurekareka.
Kei roto nga korero mo te mana whakamohoatanga o te waahanga IP.
Ko te whakaurunga e hiahiatia ana file mo te ip-make-simscript ki te whakaputa tuhinga whaihanga mo nga simulators tautoko. Ko te .spd file kei roto he rarangi o files hangaia mo te whaihanga, me nga korero mo nga mahara ka taea e koe te arawhiti.
Ka taea e koe te whakamahi i te pouaka-pango Verilog (_bb.v) file hei whakapuakanga kōwae putua hei whakamahi hei pouaka pango.
HDL exampte tauira inamata. Ka taea e koe te kape me te whakapiri i nga ihirangi o tenei file ki to HDL file ki te whakatika i te rereketanga IP.
Mena kei roto i te IP nga korero rehita, .regmap file whakaputa. Ko te .regmap file he whakaahua i nga korero mapi rehita o nga atanga ariki me te taurekareka. Tenei file ka whakakiia te .sopcinfo file ma te whakarato i nga korero mo te rehita mo te punaha. Ma tenei ka taea te whakaatu rehita views me nga tatauranga ka taea e te kaiwhakamahi ki te Papatohu Pūnaha.
Tukua nga taputapu Patuiro Pūnaha (HPS) ki te view nga mapi rehita o nga papaahiko e hono ana ki te HPS i roto i te punaha Kaihoahoa Papaaho. I te wa o te whakahiatotanga, ko te .svd files mo nga atanga taurekareka e kitea ana e nga rangatira o te Papatohu Pūnaha kei te rongoa i roto i te .sof file i te wahanga patuiro. Ka panuihia e te Papatohu Pūnaha tenei waahanga, ka taea e te Kaihoahoa Platform te patai mo te rehitatanga o nga korero mahere. Mo nga pononga punaha, ka taea e te Kaihoahoa Platform te uru ki nga rehita ma te ingoa.
HDL files e whakamohio ana i ia waahanga iti, IP tamaiti ranei mo te whakahiato me te whaihanga.
Kei roto he tauira ModelSim*/QuestaSim* msim_setup.tcl hei whakarite me te whakahaere i te whaihanga.
Kei roto he tuhinga anga vcs_setup.sh hei whakarite me te whakahaere i te whaihanga VCS*. Kei roto he tuhinga anga vcsmx_setup.sh me synopsys_sim.setup file ki te whakarite me te whakahaere i te whaihanga VCS MX.
Kei roto he tuhinga anga xcelium_setup.sh me etahi atu tatūnga files ki te whakarite me te whakahaere Xcelium* whaihanga.
He HDL kei roto files mo nga waahanga iti IP.
Mo ia whaiaronga IP tamaiti kua hangaia, ka hangaia e te Kaihoahoa Platform te synth/me te sim/tohu-iti.

3.4. Te whakatauira i nga Core IP FPGA Intel
Ko te rorohiko Intel Quartus Prime e tautoko ana i te whaihanga IP matua RTL i roto i nga miihini EDA motuhake. Ko te whakatipuranga IP ka taea te hanga whaihanga files, tae atu ki te tauira whaihanga mahi, tetahi papa whakamatautau (exampte hoahoa), me nga tuhinga tatūnga simulator motuhake mo ia kaupapa IP. Ka taea e koe te whakamahi i te tauira whaihanga mahi me tetahi papa whakamatautau, o mua raneiampte hoahoa mo te whaihanga. Ko nga putanga whakangao IP ka uru ano ki nga tuhinga hei whakahiato me te whakahaere i nga waahi whakamatautau. Ka whakarārangihia e ngā hōtuhi ngā tauira katoa, whare pukapuka rānei e hiahia ana koe ki te whakataurite i to matua IP.

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Ko te rorohiko Intel Quartus Prime e whakarato ana i te whakaurunga me te maha o nga simulators me te tautoko i te maha o nga rerenga whaihanga, tae atu ki a koe ake i te tuhi me nga rerenga whaihanga ritenga. Ahakoa te rere e whiriwhiria e koe, ko te whaihanga IP matua e whai ake nei:
1. Hangaia te IP HDL, te pae whakamatautau (meheampte hoahoa), me te tuhinga tatūnga simulator files.
2. Whakaritehia to taiao simulator me etahi tuhinga whaihanga.
3. Whakahiato whare pukapuka tauira whaihanga.
4. Whakahaerehia to simulator.

3.4.1. Te Whakatau me te Manatoko i te Hoahoa

Ma te taunoa, ka hangaia e te ētita tawhā he tuhinga motuhake-simulatoru kei roto nga whakahau hei whakahiato, whakahiato me te whakataurite i nga tauira Intel FPGA IP me te whare pukapuka tauira whaihanga. files. Ka taea e koe te kape i nga whakahau ki roto i to tuhinga whakamaarama whakamatautau, whakatika ranei i enei files ki te taapiri i nga whakahau mo te whakahiato, te whakamaarama me te whakataurite i to hoahoa me to papa whakamatautau.

Ripanga 10. Intel FPGA IP Core Simulation Scripts

Simulator

File Whaiaronga

TauiraSim

_sim/tautohu

QuestaSim

VCS

_sim/synopsys/vcs

VCS MX

_sim/synopsys/vcsmx

Xcelium

_sim/xcelium

Hōtuhi msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Te whakahiato i nga Utauta IP ki etahi atu Utauta EDA
Ka taea, whakamahia tetahi atu taputapu EDA e tautokohia ana ki te whakahiato i tetahi hoahoa kei roto nga matua Intel FPGA IP. Ka whakaputa koe i te whakahiatotanga matua IP files mo te whakamahi me nga taputapu whakahiato EDA tuatoru, ka taea e koe te hanga i tetahi rarangi kupenga whakatau tata me te waahi. Hei whakaahei i te reanga, whakakāhia te Waihanga wa me te whakatau tata rauemi mo nga taputapu whakahiato EDA tuatoru ina whakarite i to rerekeetanga IP.
Ko te rarangi whakatau tata rohe me te wa e whakaatu ana i te hononga matua IP me te hoahoanga, engari kaore he korero mo te mahi pono. Ma enei korero ka taea e etahi taputapu whakahiato-tuatoru te pai ake te whakaatu i nga whakatau tata o te waahi me te wa. I tua atu, ka taea e nga taputapu whakahiato te whakamahi i nga korero mo te waa ki te whakatutuki i nga arotautanga a te waa me te whakapai ake i te kounga o nga hua.
Ko te rorohiko Intel Quartus Prime te whakaputa i te _syn.v netlist file i roto i te hōputu Verilog HDL, ahakoa te putanga file whakatakotoranga ka tohua e koe. Mena ka whakamahi koe i tenei rarangi ipurangi mo te whakahiato, me whakauru koe i te takai matua IP file .v ranei .vhd i roto i to kaupapa Intel Quartus Prime.

(7) Ki te kore koe i whakarite i te whiringa taputapu EDA– ka taea e koe te timata i nga simulators EDA tuatoru mai i te rorohiko Intel Quartus Prime–whakahaerehia tenei tuhinga ki te papatohu ModelSim, QuestaSim simulator Tcl ranei (kaore i te rorohiko Intel Quartus Prime. Tcl console) hei karo i nga hapa.

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3.6. Te whakahiato i te Hoahoa Katoa
Ka taea e koe te whakamahi i te whakahau Timata Whakahiato i te tahua Tukatuka i roto i te rorohiko Intel Quartus Prime Pro Edition hei whakahiato i to hoahoa.

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4. Whakaahuatanga Mahi

Whakaahua 5.

F-Tile Serial Lite IV Intel FPGA IP he MAC me Ethernet PCS. Ka whakawhitiwhiti te MAC ki nga PCS ritenga na roto i nga hononga MII.

Ka tautokohia e te IP nga momo whakarereke e rua:
· PAM4–He 1 ki te 12 te maha o nga huarahi hei whiriwhiri. I nga wa katoa ka tukuna e te IP nga hongere PCS e rua mo ia ara i te aratau whakarereke PAM4.
· NRZ–He 1 ki te 16 te maha o nga huarahi hei whiriwhiri.

Ka tautokohia e ia aratau whakarereke nga aratau raraunga e rua:
· Aratau Taketake–He aratau roma parakore tenei ka tukuna nga raraunga me te kore te tiimata-pakete, te hurihanga kau, me te mutunga-o-pakete hei whakanui i te bandwidth. Ka tangohia e te IP nga raraunga whaimana tuatahi hei timatanga o te pakaru.

Whakawhiti Raraunga Aratau Taketake tx_core_clkout tx_avs_ready

tx_avs_mana tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 Kua Rehitatia

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Whakaahua 6.

· Aratau katoa–Koinei te whakawhiti raraunga aratau paakete. I tenei aratau, ka tukuna e te IP he pakaru me te huringa tukutahi i te timatanga me te mutunga o te paatete hei kaiwehe.

Whakawhiti Raraunga Aratau Katoa tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Nga korero e pa ana · F-Tile Serial Lite IV Intel FPGA IP Overview i te wharangi 6 · F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

4.1. TX Raraunga Raraunga
Ko te ara raraunga TX ko nga waahanga e whai ake nei: · MAC adapter · Mana whakahaere paraka whakauru kupu · CRC · MII encoder · PCS paraka · PMA paraka

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Whakaatu 7. TX Raraunga Raraunga

Mai i te arorau kaiwhakamahi

TX MAC

Avalon Streaming Atanga

MAC Whāurutau

Whakahaere Kupu Whakauru

CRC

MII Encoder

MII Atanga Ritenga PCS
PCS me PMA

TX Atanga Rangatū Ki Ētahi Atu Pūrere FPGA

4.1.1. TX MAC Whāurutau
Ko te TX MAC adapter e whakahaere ana i te tuku raraunga ki te arorau kaiwhakamahi ma te whakamahi i te atanga roma Avalon®. Ko tenei poraka e tautoko ana i te tuku korero me te whakahaere rere.

Te whakawhiti i nga korero kua tautuhia e te Kaiwhakamahi

I roto i te aratau Katoa, ka whakaratohia e te IP te tohu tx_is_usr_cmd ka taea e koe te whakamahi hei timata i te huringa korero kua tautuhia e te kaiwhakamahi penei i te tuku XOFF/XON ki te arorau kaiwhakamahi. Ka taea e koe te timata i te huringa whakawhiti korero kua tautuhia e te kaiwhakamahi ma te whakaatu i tenei tohu me te whakawhiti i nga korero ma te whakamahi i te tx_avs_data me te whakapae o tx_avs_startofpacket me nga tohu tx_avs_valid. Ka whakakorehia e te poraka te tx_avs_ready mo nga huringa e rua.

Tuhipoka:

Ko te waahanga korero kua tautuhia e te kaiwhakamahi e waatea ana i te aratau Katoa.

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Whakaahua 8.

Mana Rere

He tikanga kaore te TX MAC i reri ki te whiwhi raraunga mai i te arorau a te kaiwhakamahi penei i te wa o te huringa hono hono, kaore ranei he raraunga e waatea ana mo te tuku mai i te arorau kaiwhakamahi. Hei karo i te ngaronga raraunga na enei tikanga, ka whakamahia e te IP te tohu tx_avs_ready ki te whakahaere i te rerenga raraunga mai i te arorau kaiwhakamahi. Ka whakakorehia e te IP te tohu ina puta nga ahuatanga e whai ake nei:
· Ina whakatauhia te tx_avs_startofpacket, ka whakakorehia te tx_avs_ready mo te huringa karaka kotahi.
· Ina whakatauhia te tx_avs_endofpacket, ka whakakorehia te tx_avs_ready mo te huringa karaka kotahi.
· I te wa e kii ana nga CW takirua ka whakakorea te tx_avs_ready mo nga huringa karaka e rua.
· I te wa e whakaurua ana te tohu tohu whakatika RS-FEC ki te atanga PCS ritenga, ka whakakorehia te tx_avs_ready mo nga huringa karaka e wha.
· Ia 17 huringa karaka matua Ethernet i roto i te aratau whakarereke PAM4 me ia huringa karaka matua 33 Ethernet i roto i te aratau whakarereke NRZ. Kua whakakorehia te tx_avs_ready mo te huringa karaka kotahi.
· Ka mutu te arorau a te kaiwhakamahi i te tx_avs_valid i te wa kaore he tuku raraunga.

Ko nga hoahoa wa e whai ake nei he exampte iti o te TX MAC urutau ma te whakamahi i te tx_avs_ready mo te whakahaere rerenga raraunga.

Mana Rere me te tx_avs_valid Deassertion me te START/END CW Paihere

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Nga tohu tohu whaimana

D5 D6

tx_avs_ready tx_avs_startofpacket

Kua reri nga tohu tohu mo nga huringa e rua hei whakauru i te END-STRT CW

tx_avs_endofpacket

usrif_raraunga

D1 D2 D3

CW_raraunga

DN MUTU STRT D0 D1 D2 D3 PUUTU D4

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Whakaahua 9.

Mana Rere me te Whakauru Tohu Tirohanga
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN DN+1

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Whakaahua 10.

Mana Rere me te TIMA/MUTUNGA Nga CW Taurua Ka Taurite ki te Whakauru Tohu Whakaata

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_raraunga

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 MUTU STRT D0

CW_raraunga

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 MUTU STRT D0

CRC_raraunga

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 MUTU STRT D0

MII_raraunga

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 MUTU STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

WHAKAMUTU STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Whakauru Kupu Mana (CW).
Ka hangaia e te F-Tile Serial Lite IV Intel FPGA IP nga CW i runga i nga tohu whakauru mai i te arorau kaiwhakamahi. Ko nga CWs e tohu ana i nga kaiwehenga paatete, nga korero mana tuku, nga raraunga kaiwhakamahi ranei ki te poraka PCS a ka ahu mai i nga waehere mana XGMII.
Ko te ripanga e whai ake nei e whakaatu ana i te whakaahuatanga o nga CW e tautokohia ana:

Tuku Urupare

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Ripanga 11.
WHAKATAKI WHAKAMUTUNGA

Whakaahuatanga o CWs Tautokohia

Te maha o nga kupu (1 kupu

= 64 moka)

EMPTY_CYC

IDLE

Kao

RARAUNGA

I roto i te roopu

Whakaahuatanga
Te timatanga o te kaiwehe raraunga. Whakamutunga o te kaiwehe raraunga. Kupu whakahaere (CW) mo te tirohanga RX. Te huringa putua i roto i te whakawhiti raraunga. IDLE (kei waho o te roopu). Utauta.

Ripanga 12. CW Field Description
Āpure RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Whakaahuatanga
mara kua rahuitia. Ka taea te whakamahi mo te toronga a meake nei. Kua herea ki te 0.
Te maha o nga paita whaimana i te kupu whakamutunga (64-bit). He uara moka-3 tenei. · 3'b000: 8 paita · 3'b001: 1 paita · 3'b010: 2 paita · 3'b011: 3 paita · 3'b100: 4 paita · 3'b101: 5 paita · 3'b110: 6 paita · 3'b111: 7 paita
Te maha o nga kupu kore-tika i te mutunga o te pakaru.
E tohu ana i te atanga romaroma RX Avalon hei whakaatu i te tohu mutunga-o-pakete.
Ka tohu i te atanga romaroma RX Avalon ki te kii i te tohu tiimata-o-pakete.
Ka tohu i te atanga romaroma RX Avalon ki te kii i te tiimata-o-te-pakete me te mutunga-o-pakete i roto i te huringa kotahi.
Tirohia te tirohanga RX.
Ko nga uara o te CRC kua tohua.
E tohu ana kei roto i te kupu mana (CW) nga korero kua tautuhia e te kaiwhakamahi.

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4.1.2.1. CW timata-o te pakaru

Whakaaturanga 11. Hōputu CW Tīmata-o-pakaru

Timata

63:56

RSVD

55:48

RSVD

47:40

RSVD

raraunga

39:32 31:24

RSVD RSVD

23:16

sop usr align=0 seop

15:8

hongere

7:0

'hFB(TMATA)

mana 7:0

Ripanga 13.

I te aratau Katoa, ka taea e koe te whakauru i te START CW ma te whakaatu i te tohu tx_avs_startofpacket. Ka whakatauhia e koe te tohu tx_avs_startofpacket anake, ka whakatauhia te moka sop. Ka whakatauhia e koe nga tohu tx_avs_startofpacket me tx_avs_endofpacket, kua tautuhia te moka seop.

Tīmatahia nga Uara Apure CW
Sop/seop mara
usr (8)
whakahāngai

Uara

I runga i te tohu tx_is_usr_cmd:

1: Ina tx_is_usr_cmd = 1

0: Ina tx_is_usr_cmd = 0

I roto i te aratau Basic, ka tukuna e te MAC he START CW i muri i te whakakore i te tautuhi. Mena karekau he raraunga, ka tukuna tonutia e te MAC EMPTY_CYC e hono ana me nga END me te START CW kia timata ra ano koe ki te tuku raraunga.

4.1.2.2. Whakamutunga o te pakaru CW

Whakaahua 12. Whakamutunga-o-pakaru CW Hōputu

MUTU

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

raraunga 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

PUTANGA

7:0

RSVD

num_valid_bytes_eob

mana whakahaere

7:0

(8) Ka tautokohia tenei i te aratau Katoa.
Tuku Urupare

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Ripanga 14.

Ka whakauruhia e te MAC te END CW i te wa e kii ana te tx_avs_endofpacket. Kei te END CW te maha o nga paita whaimana i te kupu raraunga whakamutunga me nga korero CRC.

Ko te uara CRC he hua CRC 32-bit mo nga raraunga i waenga i te START CW me te kupu raraunga i mua i te END CW.

Ko te ripanga e whai ake nei e whakaatu ana i nga uara o nga mara i END CW.

END CW Uara mara
Āpure eop CRC32 num_valid_bytes_eob

Uara 1
CRC32 uara tatau. Te maha o nga paita whaimana i te kupu raraunga whakamutunga.

4.1.2.3. Tirohanga Paired CW

Whakaaturanga 13. Whakaritenga Whakahoahoa CW

WHAKATAHIA CW Takirua ki te TIMA/MUTU

64+8bits XGMII Atanga

Timata

63:56

RSVD

55:48

RSVD

47:40

RSVD

raraunga

39:32 31:24

RSVD RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

RSVD

7:0

'hFB

mana 7:0

64+8bits XGMII Atanga

MUTU

63:56

'hFD

55:48

RSVD

47:40

RSVD

raraunga

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

mana 7:0

Ko te ALIGN CW he CW takirua me nga CW START/END, END/START ranei. Ka taea e koe te whakauru i te CW takirua ALIGN ma te tohu i te tohu tx_link_reinit, te tautuhi i te porotiti Wā Whakaritenga, me te whakaara ano ranei. Ina whakaurua te ALIGN takirua CW, ka tautuhia te apure tiaro ki te 1 hei timata i te paraka tiaroaro kaiwhiwhi ki te tirotiro i te tirohanga raraunga puta noa i nga huarahi katoa.

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Ripanga 15.

WHAKAARO Nga Uara Apure CW
Tirohanga mara
eop sop usr seop

Uara 1 0 0 0 0

4.1.2.4. Hurihanga Putua CW

Whakaahua 14. Huringa CW Putua-puua

EMPTY_CYC Tauhoa ki te END/START

64+8bits XGMII Atanga

MUTU

63:56

'hFD

55:48

RSVD

47:40

RSVD

raraunga

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

mana 7:0

64+8bits XGMII Atanga

Timata

63:56

RSVD

55:48

RSVD

47:40

RSVD

raraunga

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

RSVD

7:0

'hFB

mana 7:0

Ripanga 16.

Ka whakakorehia e koe te tx_avs_valid mo nga huringa karaka e rua i te wa e pakaru ana, ka whakauruhia e te MAC he EMPTY_CYC CW e hono ana ki nga CW END/START. Ka taea e koe te whakamahi i tenei CW karekau he raraunga e waatea ana mo te tuku mo te wa poto.

Ina whakakorehia e koe te tx_avs_valid mo te huringa kotahi, ka whakakorehia e te IP te tx_avs_valid mo te rua o te waa o te tx_avs_valid deassertion hei whakaputa i te rua o nga END/START CWs.

EMPTY_CYC CW Uara mara
Tirohanga mara
eop

Uara 0 0

haere tonu…

Tuku Urupare

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Field sop usr seop

Uara 0 0 0

4.1.2.5. CW mangere

Whakaatu 15. Hōputu CW Idle

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

raraunga

39:32 31:24

'h07 'h07

23:16

'h07

15:8

'h07

7:0

'h07

mana 7:0

Ka whakauruhia e te MAC te IDLE CW i te wa kaore he tuku. I tenei wa, he iti te tohu tx_avs_valid.
Ka taea e koe te whakamahi i te IDLE CW ina oti te whakawhitinga pakaru, kei te noho mangere ranei te tuku.

4.1.2.6. Kupu Raraunga

Ko te kupu raraunga ko te utu o te kete. Ko nga moka whakahaere XGMII kua whakaritea katoa ki te 0 i te whakatakotoranga kupu raraunga.

Whakaahua 16. Raraunga Kupu Raraunga

64+8 paraka XGMII Atanga

KUPU RARAUNGA

63:56

raraunga kaiwhakamahi 7

55:48

raraunga kaiwhakamahi 6

47:40

raraunga kaiwhakamahi 5

raraunga

39:32 31:24

raraunga kaiwhakamahi 4 raraunga kaiwhakamahi 3

23:16

raraunga kaiwhakamahi 2

15:8

raraunga kaiwhakamahi 1

7:0

raraunga kaiwhakamahi 0

mana 7:0

4.1.3. TX CRC
Ka taea e koe te whakahohe i te poraka TX CRC ma te whakamahi i te tawhā Whakahohe CRC i roto i te Kaiwhakatika Tawhā IP. Ka tautokohia tenei ahuatanga i roto i nga momo Tika me te Katoa.

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Ka taapirihia e te MAC te uara CRC ki te END CW ma te whakapae i te tohu tx_avs_endofpacket. I roto i te aratau BASIC, ko te ALIGN CW anake e hono ana ki te END CW kei roto he mara CRC whaimana.
Ko te TX CRC poraka atanga ki te TX Control Word Insertion me te TX MII Encode paraka. Ko te paraka TX CRC e tatau ana i te uara CRC mo te 64-bit uara mo ia-huringa raraunga timata mai i te START CW ki te END CW.
Ka taea e koe te kii i te tohu crc_error_inject ki te whakakino i nga raraunga i roto i tetahi ara motuhake hei hanga hapa CRC.

4.1.4. TX MII Encoder

Ko te encoder TX MII e whakahaere ana i te tuku paakete mai i te MAC ki te TX PCS.

Ko te ahua e whai ake nei e whakaatu ana i te tauira raraunga i runga i te pahi 8-bit MII i te aratau whakarereke PAM4. Ko te TIMA me te WHAKAMUTU CW ka puta kotahi i ia rua ara MII.

Whakaatu 17. PAM4 Whakatauira Tauira Raraunga MII

HIKI 1

HIKI 2

HIKI 3

HIKI 4

HIKI 5

SOP_CW

RARAUNGA_1

RARAUNGA_9 RARAUNGA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

RARAUNGA_2 RARAUNGA_3 RARAUNGA_4

RARAUNGA_10 RARAUNGA_11 RARAUNGA_12

RARAUNGA_18 RARAUNGA_19 RARAUNGA_20

EOP_CW IDLE
EOP_CW

SOP_CW

RARAUNGA_5 RARAUNGA_13 RARAUNGA_21

IDLE

RARARANGA_DUMMY_6 RARAUNGA_14 RARAUNGA_22 EOP_CW

SOP_CW DATA_DUMMY

RARAUNGA_7 RARAUNGA_8

RARAUNGA_15 RARAUNGA_16

RARAUNGA_23 RARAUNGA_24

IDLE EOP_CW

Ko te ahua e whai ake nei e whakaatu ana i te tauira raraunga i runga i te pahi 8-bit MII i te aratau whakarereke NRZ. Ka puta te TIMA me te WHAKAMUTU CW ki ia ara MII.

Tuku Urupare

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Whakaatu 18. NRZ Modulation Aratau MII Tauira Raraunga

HIKI 1

HIKI 2

HIKI 3

SOP_CW

RARAUNGA_1

RARAUNGA_9

SOP_CW

RARAUNGA_2 RARAUNGA_10

SOP_CW SOP_CW

RARAUNGA_3 RARAUNGA_4

RARAUNGA_11 RARAUNGA_12

SOP_CW

RARAUNGA_5 RARAUNGA_13

SOP_CW

RARAUNGA_6 RARAUNGA_14

SOP_CW

RARAUNGA_7 RARAUNGA_15

SOP_CW

RARAUNGA_8 RARAUNGA_16

HIKI 4 RARAUNGA_17 RARAUNGA_18 RARAUNGA_19 RARAUNGA_20 RARAUNGA_21 RARAUNGA_22 RARAUNGA_23 RARAUNGA_24

HIKI 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS me PMA
Ko te F-Tile Serial Lite IV Intel FPGA IP e whirihora ana i te whakawhiti F-tile ki te aratau Ethernet PCS.

4.2. RX Raraunga
Ko te ara raraunga RX nga waahanga e whai ake nei: · Paraka PMA · Paraka PCS · Kaiwaehere MII · CRC · Paraka Deskew · Paraka tango Kupu Mana

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Whakaatu 19. RX Raraunga Raraunga

Ki te arorau kaiwhakamahi Avalon Streaming Atanga
RX MAC
Mana Tango Kupu
Deskew

CRC

MII Pūwaehere

MII Atanga Ritenga PCS
PCS me PMA

RX Atanga Rangatū Mai i etahi atu Pūrere FPGA
4.2.1. RX PCS me PMA
Ko te F-Tile Serial Lite IV Intel FPGA IP e whirihora ana i te whakawhiti F-tile ki te aratau PCS Ethernet.
4.2.2. RX MII Pūwaehere
Ka tautuhia e tenei paraka mena kei roto i nga raraunga taumai he kupu mana me nga tohu whakatika. Ko te RX MII pūwetewaehere whakaputa raraunga i te ahua o te 1-bit whaimana, 1-bit tohu tohu, 1bit mana tohu, me te 64-bit raraunga mo ia ara.
4.2.3. RX CRC
Ka taea e koe te whakahohe i te poraka TX CRC ma te whakamahi i te tawhā Whakahohe CRC i roto i te Kaiwhakatika Tawhā IP. Ka tautokohia tenei ahuatanga i roto i nga momo Tika me te Katoa. Ko te RX CRC poraka atanga ki te RX Mana Word Tangohanga me RX MII pūwetewaehere poraka. Ko te IP e kii ana i te tohu rx_crc_error ka puta he hapa CRC.

Tuku Urupare

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Ka whakakorehia e te IP te rx_crc_error i ia pakaru hou. He putanga ki te arorau kaiwhakamahi mo te whakahaere hapa arorau kaiwhakamahi.
4.2.4. RX Deskew
Ka kitea e te poraka RX deskew nga tohu whakamaarama mo ia ara me te whakahou ano i nga raraunga i mua i te tuku ki te poraka tango RX CW.
Ka taea e koe te kowhiri ki te tuku i te matua IP ki te whakahāngai aunoa i nga raraunga mo ia ara ina puta he hapa tirohanga ma te tautuhi i te tawhā Whakahohe Whakatika Aunoa i roto i te Kaiwhakatika tawhā IP. Mena ka whakakorehia e koe te waahanga whakatikatika aunoa, ka kii te matua IP i te tohu rx_error hei tohu i te hapa tirohanga. Me whakaū koe i te rx_link_reinit ki te kōkiri i te hātepe tīaroaro ara ina puta he hapa tīaroaro.
Ka kitea e te RX deskew nga tohu whakatikatika i runga i te miihini whenua. Ko te hoahoa e whai ake nei e whakaatu ana i nga ahuatanga kei roto i te poraka RX deskew.

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Tuku Urupare

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Whakaahua 20.

RX Deskew Lane Tirohanga Mīhini State me te Whakahohe Aunoa Whakahohe Tūtohi Rere
Tīmata

IDLE

Tautuhi = 1 ae kao

PCS katoa

kahore

kua rite nga huarahi?

āe

TAARI

Katoa nga tohu tukutahi no
kitea?
āe
HE WHAKAMAHI

kahore
āe Wā wā?

āe
Kua ngaro te tirohanga?
kahore he Whakamutunga

Tuku Urupare

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Whakaahua 21.

RX Deskew Lane Tirohanga Mīhini Kāwanatanga me te Tirohanga Aunoa i Monohia te Rere Tutohi
Tīmata

IDLE

Tautuhi = 1 ae kao

PCS katoa

kahore

kua rite nga huarahi?

āe

āe
rx_link_reinit =1
kore HAPA

kao ae Whetu?

TAARI
kore Katoa nga tohu tukutahi
kitea?
ae WHAKARITENGA

āe
Kua ngaro te tirohanga?
kahore
Whakamutunga
1. Ka timata te tukanga tirohanga ki te ahua IDLE. Ka neke te paraka ki te ahua WAIT ina rite nga huarahi PCS katoa ka mutu te rx_link_reinit.
2. I roto i te ahua WAIT, ka tirohia e te paraka nga tohu katoa kua kitea i roto i te huringa kotahi. Mena he pono tenei ahuatanga, ka neke te poraka ki te ahua ARA.
3. I te wa e noho ana te poraka i roto i te ahua WHAKAARO, e tohu ana kei te tiaro nga huarahi. I roto i tenei ahua, kei te haere tonu te poraka ki te aro turuki i te rarangi ara me te tirotiro mena kei te noho nga tohu katoa i roto i te huringa kotahi. Mena karekau kia kotahi te tohu i roto i te huringa kotahi ka whakatauhia te tawhā Whakahohe Tirohanga Aunoa, ka haere te paraka ki te

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 34

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4. Whakaahuatanga Mahi 683074 | 2022.04.28

Ko te ahua IDLE hei whakaara ano i te tukanga tirohanga. Ki te kore te Whakahohe Tirohanga Aunoa karekau he tohu kotahi i te huringa kotahi, ka haere te paraka ki te ahua HAPA ka tatari mo te arorau a te kaiwhakamahi ki te kii i te tohu rx_link_reinit ki te timata i te huarahi whakatikatika ara.

Whakaahua 22. Te Whakaritea Rarangi me te Whakahohe Tirohanga Aunoa Whakahohe rx_core_clk

rx_link_up

rx_link_reinit

me_katoa_tohu

Whenua Deskew

WHAKAARO

IDLE

TAARI

WHAKAARO

AUTO_ALIGN = 1

Whakaatu 23. Te Whakaritea Rarangi me te Whakahohe Tirohanga Aunoa Kua Mono rx_core_clk

rx_link_up

rx_link_reinit

me_katoa_tohu

Whenua Deskew

WHAKAARO

HAPA

IDLE

TAARI

WHAKAARO

AUTO_ALIGN = 0
4.2.5. RX CW Tangohanga
Ka whakakorehia e tenei poraka nga CW me te tuku raraunga ki te arorau kaiwhakamahi ma te whakamahi i te atanga roma Avalon i muri i te tangohanga o nga CW.
Karekau he raraunga whaimana e waatea ana, ka whakakorehia e te poraka tango RX CW te tohu rx_avs_valid.
I roto i te aratau FULL, ki te whakatauhia te moka kaiwhakamahi, ka kii tenei poraka i te tohu rx_is_usr_cmd me nga raraunga i te huringa karaka tuatahi ka whakamahia hei korero kua tautuhia e te kaiwhakamahi, hei whakahau ranei.
A, no te rx_avs_ready deasserts me rx_avs_valid asserts, te RX CW poraka tango hanga he huru hapa ki te arorau kaiwhakamahi.
Ko nga tohu rerema Avalon e pa ana ki tenei poraka e whai ake nei: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (e waatea ana i te aratau Katoa)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
Ko te F-Tile Serial Lite IV Intel FPGA IP e wha nga whakaurunga karaka e whakaputa karaka ki nga poraka rereke: · Karaka tohutoro whakawhiti (xcvr_ref_clk)–Karaka whakauru mai i te karaka o waho
maramara ranei oscillators e whakaputa karaka mo TX MAC, RX MAC, me TX me RX poraka PCS ritenga. Tirohia nga Tawhā mo te awhe auau tautoko. · Karaka matua TX (tx_core_clk)–I ahu mai tenei karaka mai i te transceiver PLL e whakamahia ana mo TX MAC. Ko tenei karaka he karaka whakaputa mai i te F-tile transceiver hei hono atu ki te arorau kaiwhakamahi TX. · RX matua karaka (rx_core_clk)–I ahu mai tenei karaka i te transceiver PLL e whakamahia ana mo te RX deskew FIFO me RX MAC. Ko tenei karaka he karaka whakaputa mai i te whakawhiti F-tile hei hono atu ki te arorau kaiwhakamahi RX. · Karaka mo te atanga whirihoranga whakawhiti whakawhiti (reconfig_clk)–whakauru karaka mai i nga karaka karaka o waho, oscillators ranei e whakaputa karaka mo te atanga whirihora whakawhiti whakawhiti F-tile i roto i nga ara raraunga TX me RX. Ko te auau karaka ko te 100 ki te 162 MHz.
Ko te hoahoa poraka e whai ake nei e whakaatu ana i nga rohe karaka F-Tile Serial Lite IV Intel FPGA IP me nga hononga i roto i te IP.

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 36

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Whakaahua 24.

F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Atanga Atanga Karaka
(whakahou_clk)

tx_core_clkout (hono ki te arorau kaiwhakamahi)

tx_core_clk= clk_pll_div64[waenganui_ch]

FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Karaka Atanga Atanga Whakawhitiwhiti

(whakahou_clk)

Oscillator

rx_core_clk= clk_pll_div64[waenganui_ch]

rx_core_clkout (hono ki te arorau kaiwhakamahi)

clk_pll_div64[waenganui_ch] clk_pll_div64[n-1:0]

Avalon Streaming Atanga TX Raraunga
TX MAC

hono_rangatū[n-1:0]

Deskew

FIFO

Avalon Streaming Atanga RX Raraunga RX MAC

Avalon Streaming Atanga RX Raraunga
RX MAC

Deskew FIFO

rx_core_clkout (hono ki te arorau kaiwhakamahi)

rx_core_clk= clk_pll_div64[waenganui_ch]

PCS Ritenga

hono_rangatū[n-1:0]

TX MAC

Avalon Streaming Atanga TX Raraunga

tx_core_clk= clk_pll_div64[waenganui_ch]

tx_core_clkout (hono ki te arorau kaiwhakamahi)

Karaka Whakawhiti Whakawhiti (xcvr_ref_clk)
Karaka Whakawhiti Whakawhiti (xcvr_ref_clk)

Oscillator*

Poutohu

taputapu FPGA
rohe karaka matua TX
RX rohe karaka matua
Rohe karaka tohutoro whakawhiti Waea o waho Nga tohu Raraunga

4.4. Tautuhi Anō me te Hononga Arawhiti
Ko te MAC, F-tile Hard IP, me nga poraka whirihora he rereke nga tohu tautuhi: · Ko nga poraka TX me RX MAC e whakamahi ana i nga tohu tautuhi tx_core_rst_n me rx_core_rst_n. · tx_pcs_fec_phy_reset_n me rx_pcs_fec_phy_reset_n puku tohu tautuhi
te kaiwhakahaere tautuhi ngohengohe ki te tautuhi i te F-tile Hard IP. · Ka whakamahia e te poraka whirihoranga te tohu reconfig_reset.

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Whakaahua 25. Tautuhi Ahuatanga
Avalon Streaming Atanga TX Raraunga
MAC
Avalon Streaming SYNC Interface RX Raraunga

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

F-tile IP Maamaa

TX Raraunga Raraunga RX Raraunga Raraunga

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Tautuhi Arorau
Nga korero e pa ana · Tautuhi Nga Aratohu i te wharangi 51 · F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi
4.4.1. TX Tautuhi me te Raupapa Arawhiti
Ko te raupapa tautuhi TX mo te F-Tile Serial Lite IV Intel FPGA IP e whai ake nei: 1. Whakauruhia te tx_pcs_fec_phy_reset_n, tx_core_rst_n, me te reconfig_reset
i te wa kotahi ki te tautuhi i te F-tile pakeke IP, MAC, me nga poraka whirihora. Tukua te tx_pcs_fec_phy_reset_n me te tautuhi ano i muri i te tatari mo te tx_reset_ack kia pai ai te tautuhi i nga poraka. 2. Na te IP ka kii i nga tohu phy_tx_lanes_stable, tx_pll_locked, me te phy_ehip_ready i muri i te tukunga o tx_pcs_fec_phy_reset_n reset, hei tohu kua rite te TX PHY mo te tuku. 3. Ka mutu te tohu tx_core_rst_n i muri i te tohu phy_ehip_ready ka piki ake. 4. Ka timata te IP ki te tuku i nga tohu IDLE i runga i te atanga MII ina mutu ana te tautuhi i te MAC. Karekau he whakaritenga mo te whakatiaroaro o te ara TX me te whiria na te mea he kotahi te karaka e whakamahia ana e nga huarahi katoa. 5. I te wa e tuku ana nga tohu IDLE, ka kii te MAC i te tohu tx_link_up. 6. Ka timata te MAC ki te tuku i te WHAKAARO kua honoa ki te START/END, END/START CW ranei i te waahi kua whakaritea hei timata i te tukanga tirohanga ara o te kaiwhiwhi hono.

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 38

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Whakaahua 26.

TX Tautuhi me te Hoahoa Wā Momowhiti
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _maukati

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. RX Tautuhi me te Raupapa Arawhiti
Ko te raupapa tautuhi RX mo te F-Tile Serial Lite IV Intel FPGA IP e whai ake nei:
1. Whakauruhia te rx_pcs_fec_phy_reset_n, rx_core_rst_n, me te reconfig_reset i te wa kotahi ki te tautuhi i te F-tile IP pakeke, MAC, me nga poraka whirihora. Tukuna te rx_pcs_fec_phy_reset_n me te tautuhi ano i muri i te tatari mo te rx_reset_ack kia pai ai te tautuhi i nga poraka.
2. Na te IP ka kii te tohu phy_rx_pcs_ready i muri i te tukunga o te tautuhi PCS ritenga, hei tohu kua reri a RX PHY mo te tuku.
3. Ka mutu te tohu rx_core_rst_n i muri i te tohu phy_rx_pcs_ready ka piki ake.
4. Ka timata te IP i te tukanga whakatikatika ara i muri i te tukunga o te tautuhi RX MAC, a, i te wa e whiwhi ana koe i te WHAKAARO kua honoa ki te START/END, END/START CW ranei.
5. Ko te paraka RX deskew e kii ana i te tohu rx_link_up ina oti te tirohanga mo nga huarahi katoa.
6. Ko te IP ka kii i te tohu rx_link_up ki te arorau kaiwhakamahi hei tohu kua reri te hononga RX ki te timata te tango raraunga.

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Whakaatu 27. RX Reset and Initialization Time Diagram
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_raka

rx_block_lock

rx_pcs_rite

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Reiti Hononga me te Tatautanga Whainga Aratuku

Ko te F-Tile Serial Lite IV Intel FPGA IP bandwidth pai tātai i raro:

Te kaha o te aratuku = raw_rate * 64/66 * (whawhati_rahi – burst_size_ovhd)/whawhati_rahi * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period]

Ripanga 17. Whakamaramatanga Taurangi Puainga Aratuku

Taurangi

Whakaahuatanga

raw_rate pakaru_rahi

Koinei te reiti moka ka tutuki e te atanga rangatū. raw_rate = SERDES whanui * auau karaka transceiver Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Uara o te rahi pakaru. Hei tatau i te kaha o te bandwidth toharite, whakamahia te uara rahi pakaru noa. Mo te reiti teitei, whakamahia te uara rahi pakaru.

pakaru_rahi_ovhd

Te uara o runga o te rahi pakaru.
I te aratau Katoa, ko te uara burst_size_ovhd e tohu ana ki nga CW takirua START me END.
I roto i te aratau Taketake, karekau he burst_size_ovhd na te mea karekau he CW takirua START me te END.

align_marker_period

Ko te uara o te wa ka whakaurua he tohu tirohanga. Ko te uara he 81920 huringa karaka mo te whakahiato me te 1280 mo te whaihanga tere. Ka whiwhihia tenei uara mai i te arorau pakeke PCS.

align_marker_width srl4_align_period

Te maha o nga huringa karaka e mau ana te tohu tohu tirohanga tika.
Te maha o nga huringa karaka i waenga i nga tohu tirohanga e rua. Ka taea e koe te tautuhi i tenei uara ma te whakamahi i te tawhā Wā Tirohanga i te Kaiwhakatika Tawhā IP.

F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi 40

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Ko nga tatauranga reiti hono kei raro iho nei: Reeti whai hua = te pai o te bandwidth * raw_rate Ka taea e koe te tiki i te auau karaka kaiwhakamahi morahi me te wharite e whai ake nei. Ko te morahi o te tatauranga karaka karaka ka mau tonu te rerenga raraunga, kaore he huringa IDLE ka puta i te arorau a te kaiwhakamahi. He mea nui tenei reeti i te wa e hoahoa ana i te arorau kaiwhakamahi FIFO hei karo i te waipuke FIFO. Te auau karaka kaiwhakamahi teitei = reeti whai hua / 64

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5. Parameta

Ripanga 18. F-Tile Serial Lite IV Intel FPGA IP Tawhā Whakaahuatanga

Tawhā

Uara

Taunoa

Whakaahuatanga

Kōwhiringa Hoahoa Whānui

Momo whakarereke PMA

· PAM4 · NRZ

PAM4

Tīpakohia te aratau whakarereke PCS.

Momo PMA

· FHT · FGT

FGT

Ka tohua te momo whakawhiti.

PMA reiti raraunga

· Mo te aratau PAM4:
— Momo whakawhiti FGT: 20 Gbps 58 Gbps
— Momo whakawhiti FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
· Mo te aratau NRZ:
— Momo whakawhiti FGT: 10 Gbps 28.05 Gbps
— Momo whakawhiti FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Ka tautuhi i te reeti raraunga whai hua i te putanga o te kaiwhakawhitiwhiti e whakauru ana i te tuku me etahi atu taapiri. Ka tatauhia te uara e te IP ma te whakaawhiwhi ki te 1 ira i roto i te wae Gbps.

aratau PMA

· Matarua · Tx · Rx

Matarua

Mo te momo whakawhiti whakawhiti FHT, ko te ahunga tautoko he taarua anake. Mo te momo transceiver FGT, ko te ahunga tautoko ko Duplex, Tx, me Rx.

Te maha o nga PMA

· Mo te aratau PAM4:

ara

— 1 ki te 12

· Mo te aratau NRZ:

— 1 ki te 16

Tīpakohia te maha o nga huarahi. Mo te hoahoa ngawari, ko te maha o nga huarahi e tautokohia ana he 1.

PLL auau karaka tohutoro

· Mo te momo whakawhiti whakawhiti FHT: 156.25 MHz
· Mo te momo whakawhiti whakawhiti FGT: 27.5 MHz 379.84375 MHz, i runga i te reiti raraunga whakawhiti kua tohua.

· Mo te momo whakawhiti whakawhiti FHT: 156.25 MHz
· Mo te momo whakawhiti FGT: 165 MHz

Ka whakapūtā te auau karaka tohutoro o te kaiwhakawhitiwhiti.

Pūnaha PLL

—

karaka tohutoro

auau

170 MHz

Kei te waatea noa mo te momo whakawhiti whakawhiti FHT. Ka tautuhia te karaka tohutoro PLL Pūnaha ka whakamahia hei whakaurunga mo te Tohutoro F-Tile me nga Karaka PLL Pūnaha Intel FPGA IP hei whakaputa i te karaka PLL Pūnaha.

Pūnaha PLL auau
Te Wā Whakaritenga

— 128 65536

Whakahohe RS-FEC

Whakahohe

876.5625 MHz 128 Whakahohe

Ka tautuhi i te auau karaka PLL Pūnaha.
Ka whakapūtā te wā tohu tīaroaro. Me x2 te uara. Whakakā kia taea ai te āhuatanga RS-FEC.
haere tonu…

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Tawhā

Uara

Taunoa

Whakaahuatanga

Monokia

Mo te aratau whakarereke PAM4 PCS, ka taea te RS-FEC i nga wa katoa.

Atanga Kaiwhakamahi

Aratau roma

· KATOA · TATAU

Ki tonu

Tīpakohia te rerenga raraunga mo te IP.

Katoa: Ka tukuna e tenei aratau he huringa tiimata-o-pakete me te huringa mutunga-o-pakete i roto i te anga.

Taketake: He aratau roma parakore tenei ka tukuna nga raraunga me te kore he tiimata-o-pakete, kau, me te mutunga-o-te-pakete hei whakanui ake i te bandwidth.

Whakahohe CRC

Whakahohea te Monokia

Monokia

Hurihia kia taea ai te rapunga hapa CRC me te whakatika.

Whakahohehia te tirohanga aunoa

Whakahohea te Monokia

Monokia

Whakakā kia whakahohea te āhuatanga tirohanga ara aunoa.

Whakahohe i te waahi mutunga

Whakahohea te Monokia

Monokia

I te ON, kei roto i te F-Tile Serial Lite IV Intel FPGA IP he Whakamutunga Debug kua whakauruhia e hono ana ki roto ki te atanga kua mapi-maharahia a Avalon. Ka taea e te IP etahi whakamatautau me nga mahi patuiro ma JTAG te whakamahi i te Papatohu Pūnaha. Kua Weto te uara taunoa.

Te Hanumi Simplex (Kei te waatea noa tenei tautuhinga tawhā ina kowhiria e koe te hoahoa ngawari rua FGT.)

I whakahohea te RSFEC ki tetahi atu Rangatū Lite IV Simplex IP kua tuu ki te (ng) hongere FGT kotahi

Whakahohea te Monokia

Monokia

Whakakāhia tēnei kōwhiringa ki te hiahia koe i te ranunga o te whirihoranga me RS-FEC kua whakahohea me te monokia mo te F-Tile Serial Lite IV Intel FPGA IP i roto i te hoahoa simplex rua mo te aratau whakawhiti NRZ, kei reira nga TX me te RX e tuu ana ki te FGT kotahi. (ng) hongere.

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6. F-Tile Serial Lite IV Intel FPGA IP Waitohu Atanga

6.1. Tohu Karaka

Ripanga 19. Nga Tohu Karaka

Ingoa

Aronga Whanui

Whakaahuatanga

tx_core_clkout

Huaputa karaka matua TX mo te atanga PCS ritenga TX, TX MAC me nga arorau kaiwhakamahi kei roto

te ara raraunga TX.

I hangaia tenei karaka mai i te poraka PCS ritenga.

rx_core_clkout

Huaputa karaka matua RX mo te atanga PCS ritenga RX, RX deskew FIFO, RX MAC

me nga arorau kaiwhakamahi i te ara raraunga RX.

I hangaia tenei karaka mai i te poraka PCS ritenga.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Karaka tohutoro Whakawhiti Whakauru.

Ina whakaritea te momo whakawhiti ki te FGT, honoa tenei karaka ki te tohu whakaputa (out_refclk_fgt_0) o te Tohutoro F-Tile me nga Karaka PLL Pūnaha Intel FPGA IP. Ina whakaritea te momo whakawhiti ki te FHT, hono

tenei karaka ki te tohu whakaputa (out_fht_cmmpll_clk_0) o te Tohutoro F-Tile me nga Karaka PLL Pūnaha Intel FPGA IP.

Tirohia nga Tawhā mo te awhe auau tautoko.

Whakauru Karaka Whakauru mo te atanga whirihora hou whakawhiti.

Ko te auau karaka ko te 100 ki te 162 MHz.

Honoa tenei tohu karaka whakauru ki nga iahiko karaka o waho, ki nga oscillators ranei.

Whakauru Karaka Whakauru mo te atanga whirihora hou whakawhiti.

Ko te auau karaka ko te 100 ki te 162 MHz.

Honoa tenei tohu karaka whakauru ki nga iahiko karaka o waho, ki nga oscillators ranei.

out_systempll_clk_ 1

Whakauru

Karaka PLL Pūnaha.
Honoa tenei karaka ki te tohu whakaputa (out_systempll_clk_0) o te Tohutoro F-Tile me nga Karaka PLL Pūnaha Intel FPGA IP.

Ngā Tawhā Mōhiohio Pānga i te whārangi 42

6.2. Tautuhi Tohu

Ripanga 20. Tautuhi Tohu

Ingoa

Aronga Whanui

tx_core_rst_n

Whakauru

Karaka Rohe Tukutahi

rx_core_rst_n

Whakauru

Tukutahi

tx_pcs_fec_phy_reset_n 1

Whakauru

Tukutahi

Whakaahuatanga

Tohu tautuhi kaha-iti. Ka tautuhi ano i te F-Tile Serial Lite IV TX MAC.

Tohu tautuhi hohe-iti. Ka tautuhi ano i te F-Tile Serial Lite IV RX MAC.

Tohu tautuhi kaha-iti.

haere tonu…

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Ingoa

Rohe Karaka Aronga Whanui

Whakaahuatanga

Ka tautuhi ano i te F-Tile Serial Lite IV TX ritenga PCS.

rx_pcs_fec_phy_reset_n 1

Whakauru

Tukutahi

Tohu tautuhi kaha-iti. Ka tautuhi ano i nga PC ritenga F-Tile Serial Lite IV RX.

reconfig_reset

Whakauru

reconfig_clk Tohu tautuhi kaha-tiketike.

Ka tautuhi ano i te paraka whirihora atanga atanga-maamahara-a Avalon.

reconfig_sl_reset

Whakauruhia reconfig_sl_clk Tohu tautuhi-tiketike.

Ka tautuhi ano i te paraka whirihora atanga atanga-maamahara-a Avalon.

6.3. Nga Tohu MAC

Ripanga 21.

TX MAC Tohu
I tenei ripanga, ka tohu a N i te maha o nga huarahi kua whakaritea ki te ētita tawhā IP.

Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

tx_avs_ready

Putanga tx_core_clkout tohu roma Avalon.

Ka tohe, ka tohu kua rite te TX MAC ki te whakaae ki nga raraunga.

tx_avs_data

· (64*N)*2 (aratau PAM4)
· 64*N (Aratau NRZ)

Whakauru

tx_core_clkout Avalon tohu romaroma. Raraunga TX.

tx_avs_channel

Whakauruhia tx_core_clkout tohu rerema Avalon.

Te tau hongere mo nga raraunga e whakawhiti ana i te huringa o naianei.

Kaore tenei tohu i te waatea i te aratau Taketake.

tx_avs_valid

Whakauruhia tx_core_clkout tohu rerema Avalon.

Ka tohe, ka tohu he tika te tohu raraunga TX.

tx_avs_startofpacket

Whakauruhia tx_core_clkout tohu rerema Avalon.

I te wa e kii ana, ka tohu i te tiimata o te kete raraunga TX.

Whakauru mo te huringa karaka kotahi anake mo ia kete.

Kaore tenei tohu i te waatea i te aratau Taketake.

tx_avs_endofpacket

Whakauruhia tx_core_clkout tohu rerema Avalon.

Ka tohe, ka tohu te mutunga o te kete raraunga TX.

Whakauru mo te huringa karaka kotahi anake mo ia kete.

Kaore tenei tohu i te waatea i te aratau Taketake.

tx_avs_kapua

Whakauruhia tx_core_clkout tohu rerema Avalon.

Ka tohu i te maha o nga kupu kore-tika i te pakaru whakamutunga o nga raraunga TX.

Kaore tenei tohu i te waatea i te aratau Taketake.

tx_num_valid_bytes_eob

Whakauru

tx_core_clkout

He tohu i te maha o nga paita whaimana i te kupu whakamutunga o te pakaru whakamutunga. Kaore tenei tohu i te waatea i te aratau Taketake.
haere tonu…

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Ingoa tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Whānui 1
1 1
N 5

Rohe Karaka Aronga

Whakaahuatanga

Whakauru

tx_core_clkout

I te wa e kii ana, ka timata tenei tohu i tetahi huringa korero kua tautuhia e te kaiwhakamahi.
Whakauruhia tenei tohu i te huringa karaka rite ki te whakapae tx_startofpacket.
Kaore tenei tohu i te waatea i te aratau Taketake.

Putanga tx_core_clkout Ina whakahuahia, ka tohu kua reri te hononga raraunga TX mo te tuku raraunga.

Putanga

tx_core_clkout

Ka whakatauhia, ka timata tenei tohu ki te whakatikatika i nga huarahi.
Whakauruhia tenei tohu mo te huringa karaka kotahi hei whakaoho i te MAC ki te tuku i te ALIGN CW.

Whakauru

tx_core_clkout Ina whakapaehia, ka werohia e te MAC he hapa CRC32 ki nga huarahi kua tohua.

Putanga tx_core_clkout Kaore i whakamahia.

Ko te hoahoa wa e whai ake nei e whakaatu ana i te exampte o TX tuku raraunga o 10 kupu i arorau kaiwhakamahi puta noa 10 TX ara rangatū.

Whakaahua 28.

TX Whakawhitinga Raraunga Wā Hoahoa
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2, ..., 9

… N-10..

Rarangi 0

…………

STRT 0 10

N-10 MUTU STRT 0

Rarangi 1

…………

STRT 1 11

N-9 MUTU STRT 1

N-10 KAUPAPA KAUPAPA N-9 KAUPAPA KAUPAPA KAUPAPA

Rarangi 9

…………

STRT 9 19

N-1 MUTU STRT 9

N-1 KAUPAPA KAUPAPA KAUPAPA

Ripanga 22.

RX MAC Tohu
I tenei ripanga, ka tohu a N i te maha o nga huarahi kua whakaritea ki te ētita tawhā IP.

Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

rx_avs_ready

Whakaurua rx_core_clkout Avalon tohu romaroma.

I te wa e kii ana, e tohu ana kua reri te arorau kaiwhakamahi ki te whakaae raraunga.

rx_avs_data

(64*N)*2 (aratau PAM4)
64*N (Aratau NRZ)

Putanga

rx_core_clkout Avalon tohu romaroma. RX raraunga.

rx_avs_channel

Putanga rx_core_clkout tohu roma Avalon.

Ko te nama hongere mo te raraunga

riro i runga i te huringa o naianei.

Kaore tenei tohu i te waatea i te aratau Taketake.

rx_avs_valid

Putanga rx_core_clkout tohu roma Avalon.

haere tonu…

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Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

Ka tohe, ka tohu he tika te tohu raraunga RX.

rx_avs_startofpacket

Putanga rx_core_clkout tohu roma Avalon.

I te wa e kii ana, ka tohu i te tiimata o te kete raraunga RX.

Whakauru mo te huringa karaka kotahi anake mo ia kete.

Kaore tenei tohu i te waatea i te aratau Taketake.

rx_avs_endofpacket

Putanga rx_core_clkout tohu roma Avalon.

Ka tohe, ka tohu te mutunga o te kete raraunga RX.

Whakauru mo te huringa karaka kotahi anake mo ia kete.

Kaore tenei tohu i te waatea i te aratau Taketake.

rx_avs_kapua

Putanga rx_core_clkout tohu roma Avalon.

Ka tohu i te maha o nga kupu kore-tika i te pakaru whakamutunga o nga raraunga RX.

Kaore tenei tohu i te waatea i te aratau Taketake.

rx_num_valid_bytes_eob

Putanga

rx_core_clkout He tohu te maha o nga paita whaimana i te kupu whakamutunga o te pakaru whakamutunga.
Kaore tenei tohu i te waatea i te aratau Taketake.

rx_is_usr_cmd

Putanga rx_core_clkout Ina kii, ka timata tenei tohu i te kaiwhakamahi-

huringa korero kua tautuhia.

Whakauruhia tenei tohu i te huringa karaka rite ki te whakapae tx_startofpacket.

Kaore tenei tohu i te waatea i te aratau Taketake.

rx_link_up

Putanga rx_core_clkout Ina whakahuahia, ka tohu te hononga raraunga RX

kua reri mo te tango raraunga.

rx_link_reinit

Whakaurua rx_core_clkout Ina kii, ka timata tenei tohu i nga huarahi

whakahāngai anō.

Mena ka monohia e koe te Whakahohe Tirohanga Aunoa, tohua tenei tohu mo te huringa karaka kotahi hei whakaoho i te MAC ki te whakahou i nga huarahi. Mena kua tautuhia te Whakahohe Tirohanga Aunoa, ka whakatika aunoa te MAC i nga huarahi.

Kaua e kii i tenei tohu ina whakaritea te Whakahohe Tirohanga Aunoa.

rx_hapa

(N*2*2)+3 (Aratau PAM4)
(N*2)*3 (Aratau NRZ)

Putanga

rx_core_clkout

I te wa e kii ana, e tohu ana ka puta nga ahuatanga hapa i te ara raraunga RX.
· [(N*2+2):N+3] = He tohu hapa PCS mo te ara motuhake.
· [N+2] = He tohu i te hapa tirohanga. Me whakaara ano i te tirohanga ara mena ka whakatauhia tenei moka.
· [N+1]= E tohu ana ka tukuna te raraunga ki te arorau a te kaiwhakamahi karekau i rite te arorau kaiwhakamahi.
· [N] = E tohu ana i te ngaronga o te tirohanga.
· [(N-1):0] = E tohu ana kei roto te raraunga he hapa CRC.

Tuku Urupare

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6.4. Nga Tohu Whakaritenga Whakawhiti

Ripanga 23.

Nga Tohu Whakaritenga PCS
I tenei ripanga, ka tohu a N i te maha o nga huarahi kua whakaritea ki te ētita tawhā IP.

Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

reconfig_sl_panui

Whakauruhia te reconfig_sl_ PCS whirihora panui whakahau

clk

tohu.

reconfig_sl_write

Tuhia te reconfig_sl_ PCS whirihora ano

clk

tohu whakahau.

reconfig_sl_address

14 moka + clogb2N

Whakauru

reconfig_sl_ clk

Ka tautuhia te whirihora PCS i te wahitau atanga kua mapi-maharahia e Avalon i roto i te huarahi kua tohua.
He 14 nga moka mo ia ara, a ko nga moka o runga e tohu ana ki te arai whakatiki.
Example, mo te hoahoa NRZ/PAM4-4, me te reconfig_sl_address[13:0] e tohu ana ki te uara wahitau:
· reconfig_sl_address[15:1 4] whakaturia ki 00 = wāhitau mo te ara 0.
· reconfig_sl_address[15:1 4] whakaturia ki 01 = wāhitau mo te ara 1.
· reconfig_sl_address[15:1 4] whakaturia ki 10 = wāhitau mo te ara 2.
· reconfig_sl_address[15:1 4] whakaturia ki 11 = wāhitau mo te ara 3.

reconfig_sl_readdata

Putanga reconfig_sl_ Ka tautuhi i nga raraunga whirihora PCS

clk

kia panuitia e te huringa rite i roto i a

huarahi kua tohua.

reconfig_sl_waitrequest

Putanga reconfig_sl_ E tohu ana i te whirihora PCS

clk

Atanga Mahere Mahara Avalon

tohu tūpono i roto i te huarahi kua tohua.

reconfig_sl_writedata

Tāuru reconfig_sl_ Ka tautuhi i nga raraunga whirihora PCS

clk

kia tuhia ki runga i te huringa tuhi i roto i a

huarahi kua tohua.

reconfig_sl_readdata_vali

Putanga

reconfig_sl_ Whakaritea te whirihora PCS

clk

Ko nga raraunga kua riro he whaimana i roto i tetahi waahanga kua tohua

ara.

Ripanga 24.

F-Tile Nga Tohu Whakaritea Hou IP
I tenei ripanga, ka tohu a N i te maha o nga huarahi kua whakaritea ki te ētita tawhā IP.

Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

reconfig_read

Whakauruhia te reconfig_clk PMA whirihora panui panui

tohu whakahau.

reconfig_write

Whakauruhia te reconfig_clk PMA whirihora ano te tuhi

tohu whakahau.

reconfig_address

18 paraka + clog2bN

Whakauru

reconfig_clk

Ka whakapūtā te wāhitau atanga atanga kua mapi maharatia a PMA Avalon i roto i te huarahi kua tohua.
haere tonu…

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Ingoa
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Whānui
32 1 32 1

Rohe Karaka Aronga

Whakaahuatanga

I roto i nga momo PAM4 ad NRZ e rua, he 18 nga moka o ia ara, a ko nga toenga o runga e tohu ana ki te arai whakatiki.
Example, mo te hoahoa 4-ara:
· reconfig_address[19:18] whakaturia ki te 00 = wāhitau mo te ara 0.
· reconfig_address[19:18] whakaturia ki te 01 = wāhitau mo te ara 1.
· reconfig_address[19:18] whakaturia ki te 10 = wāhitau mo te ara 2.
· reconfig_address[19:18] whakaturia ki te 11 = wāhitau mo te ara 3.

Putanga

reconfig_clk Ka tautuhi i nga raraunga PMA kia panuihia e te huringa reri i roto i te huarahi kua tohua.

Putanga

reconfig_clk E tohu ana a PMA Avalon i te atanga e maumaharahia ana te atanga i te tohu aukati i tetahi huarahi kua tohua.

Whakauru

reconfig_clk Ka tautuhi i nga raraunga PMA kia tuhia ki runga i te huringa tuhi i roto i te huarahi kua tohua.

Putanga

reconfig_clk Ka tohu i te whirihora PMA kua riro nga raraunga ka whai mana ki tetahi huarahi kua tohua.

6.5. Nga Tohu PMA

Ripanga 25.

Nga Tohu PMA
I tenei ripanga, ka tohu a N i te maha o nga huarahi kua whakaritea ki te ētita tawhā IP.

Ingoa

Whānui

Rohe Karaka Aronga

Whakaahuatanga

phy_tx_lanes_stable

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Asynchronous Ina kii, e tohu ana kua reri te ara raraunga TX ki te tuku raraunga.

tx_pll_maukati

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Asynchronous I te wa e kii ana, e tohu ana kua tutuki i te TX PLL te mana maukati.

phy_ehip_ready

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Tukutahi

I te wa e kii ana, e tohu ana kua oti i te PCS te arawhitinga o roto, kua rite mo te tuku.
Ka kii tenei tohu i muri i te whakakorenga o te tx_pcs_fec_phy_reset_n me te tx_pcs_fec_phy_reset_nare.

tx_raraunga_rangatū

Huaputa TX karaka rangatū TX titi rangatū.

rx_raraunga_rangatū

Whakaurua RX karaka rangatū RX titi rangatū.

phy_rx_block_lock

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Asynchronous I te wa e kii ana, ka tohu kua oti te whakarite poraka 66b mo nga huarahi.

rx_cdr_raka

N*2 (aratau PAM4)

Putanga

Tukutahi

I te wa e kii ana, ka tohu ko nga karaka kua ora ake kua maukati ki nga raraunga.
haere tonu…

Tuku Urupare

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Ingoa phy_rx_pcs_ready phy_rx_hi_ber

Whānui

Rohe Karaka Aronga

Whakaahuatanga

N (Aratau NRZ)

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Tukutahi

I te wa e kii ana, e tohu ana ko nga huarahi RX o te hongere Itarangi e rite ana kua tino rite, kua rite ki te whiwhi raraunga.

N*2 (aratau PAM4)
N (Aratau NRZ)

Putanga

Tukutahi

I te wa e kii ana, e tohu ana ko te RX PCS o te hongere Ethernet e rite ana kei roto i te ahua HI BER.

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7. Te hoahoa me te F-Tile Serial Lite IV Intel FPGA IP

7.1. Tautuhi Arahi Aratohu
A pee i enei aratohu tautuhi ki te whakatinana i to tautuhi-a-raupapa.
· Herea nga tohu tx_pcs_fec_phy_reset_n me rx_pcs_fec_phy_reset_n ki te taumata o te punaha kia taea ai te tautuhi ano i te TX me te RX PCS i te wa kotahi.
· Whakauruhia te tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, me te reconfig_reset tohu i te wa ano. Tirohia te Tautuhi me te Hononga Arawhiti mo etahi atu korero mo te tautuhi IP me nga raupapa arawhiti.
· Puritia te tx_pcs_fec_phy_reset_n, me te rx_pcs_fec_phy_reset_n tohu iti, me te reconfig_reset tohu teitei ka tatari mo te tx_reset_ack me rx_reset_ack ki te tautuhi tika i te F-tile hard IP me nga poraka whirihora.
· Hei whakatutuki tere i te hono-ake i waenga i nga taputapu FPGA, tautuhi ano nga hononga F-Tile Serial Lite IV Intel FPGA IP i te wa ano. Tirohia te F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi mo nga korero mo te aroturuki i te hononga IP TX me RX ma te whakamahi i te kete taputapu.
Nga korero e pa ana
· Tautuhi Anō me te Hononga Arawhiti i te wharangi 37
· F-Tile Serial Lite IV Intel FPGA IP Design Exampte Aratohu Kaiwhakamahi

7.2. Nga Aratohu Whakahaere Hapa

Kei te ripanga e whai ake nei nga aratohu whakahaere hapa mo nga ahuatanga hapa ka puta pea me te hoahoa F-Tile Serial Lite IV Intel FPGA IP.

Ripanga 26. Tikanga Hapa me nga Aratohu Whakahaere

Tikanga Hapa
Kaore e taea e te kotahi, neke atu ranei nga huarahi te whakarite korero i muri i te waa kua whakaritea.

Aratohu
Whakaritea he punaha wa-waahi hei tautuhi i te hono ki te taumata tono.

Ka ngaro te whakawhitiwhiti korero i muri i te whakaturanga korero.
Ka ngaro te whakawhitiwhiti korero i tetahi ara i te wa e mahi ana.

Ka tupu pea tenei i muri i nga waahanga whakawhiti raraunga ranei. Whakatinanahia he rapunga mate hononga ki te taumata tono ka tautuhi ano i te hono.
Whakatinanahia te tukanga arataki hono mo te ara pohehe. Me whakarite kia kaua e neke ake te ararere poari i te 320 UI.

Ko te tirohanga ara ngaro i muri i te whakararangitanga o nga huarahi katoa.

Ka tupu pea tenei i muri i nga waahanga whakawhiti raraunga ranei. Whakatinanahia he rapunga ngaronga tirohanga ara i te taumata tono hei timata ano i te tukanga tirohanga ara.

ISO 9001:2015 Kua Rehitatia

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8. F-Tile Serial Lite IV Intel FPGA IP Kaiwhakamahi Aratohu Archives

He rite nga putanga IP ki nga putanga rorohiko Intel Quartus Prime Design Suite ki te v19.1. Mai i te putanga rorohiko Intel Quartus Prime Design Suite 19.2 i muri mai ranei, he kaupapa whakaputa IP hou nga konae IP.

Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.

Intel Quartus Prime Putanga
21.3

IP Core Putanga 3.0.0

Aratohu Kaiwhakamahi F-Tile Serial Lite IV Intel® FPGA IP Aratohu Kaiwhakamahi

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9. Tuhinga Tuhinga History mo te F-Tile Serial Lite IV Intel FPGA IP Aratohu Kaiwhakamahi

Tuhinga Putanga 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Putanga
22.1
21.3 21.3 21.2

Putanga IP 5.0.0
3.0.0 3.0.0 2.0.0

Huringa
· Ripanga Whakahoutia: F-Tile Serial Lite IV Intel FPGA IP Features — Whakahoutanga Whakawhiti Raraunga whakaahuatanga me etahi atu tautoko FHT transceiver reiti: 58G NRZ, 58G PAM4, me 116G PAM4
· Ripanga Whakahoutia: F-Tile Serial Lite IV Intel FPGA IP Tawhā Whakaahuatanga — Tawhā hou kua taapirihia · Te auau karaka tohutoro PLL Pūnaha · Whakahohe i te mutunga o te patuiro — Kua whakahōuhia nga Uara mo te reiti raraunga PMA — Kua whakaingoatia tawhā whakaingoatia kia rite ki te GUI
· I whakahoutia te whakaahuatanga mo te whakawhiti raraunga i te Ripanga: F-Tile Serial Lite IV Intel FPGA IP Features.
· Whakaingoatia te ingoa ripanga IP ki te F-Tile Serial Lite IV Intel FPGA IP Whakamaramatanga Tawhā i te wahanga Tawhā mo te marama.
· Ripanga Whakahoutia: Tawhā IP: — Kua taapirihia he tawhā hou–RSFEC kua whakahohea ki tetahi atu Rangatū Lite IV Simplex IP kua tuu ki te hongere FGT kotahi. — Whakahoutia nga uara taunoa mo te auau karaka tohutoro a Transceiver.
Tukunga tuatahi.

ISO 9001:2015 Kua Rehitatia

Tuhinga / Rauemi

	intel F Tile Serial Lite IV Intel FPGA IP [pdf] Aratohu Kaiwhakamahi F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Aratohu Kaiwhakamahi F-Tile Rangatū Pukapuka IV Intel FPGA IP, Rangatū Pukapuka IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP