Terenga iti E-Tapa 40G Itarangi Intel FPGA IP Hoahoa Example

Aratohu Timata Tere

Ko te E-Tile 40G Ethernet Intel® FPGA IP matua o te Latency iti e whakarato ana i tetahi papa whakamatautau whaihanga me tetahi hoahoa taputapu o mua.ampe tautoko ana i te whakahiato me te whakamatautau taputapu. Ina whakaputa koe i te hoahoa exampNa, ko te Intel Quartus® Prime IP tawhā ētita ka hanga aunoa i te files e tika ana ki te whaihanga, whakahiato, me te whakamatautau i te hoahoa i roto i te taputapu. I tua atu, ka taea e koe te tango i te hoahoa taputapu kua whakahiato ki te kete whanaketanga motuhake mo te taputapu Intel mo te whakamatautau mahi. Kei roto hoki i te Intel FPGA IP he whakahiato-anakeampte kaupapa ka taea e koe te whakamahi ki te whakatau tere i te rohe matua IP me te wa. E tautoko ana te E-Tapa iti 40G Itarangi Intel FPGA IP hoahoa exampte whakatipuranga me te whānuitanga o nga tawhā. Heoi, te hoahoa exampe kore e hipokina nga tawhā taea katoa o te Latency Iti E-Tapa 40G Itarangi Intel FPGA IP Core.

Nga Waahi Whanaketanga mo te Hoahoa Example

Nga korero e pa ana

• Terenga Iti E-Tapa 40G Itarangi Intel FPGA IP Aratohu Kaiwhakamahi
  Mo nga korero taipitopito mo te E-Tapa iti 40G Ethernet IP.
• Te Rooputanga Iti E-Tapa 40G Itarangi Intel FPGA IP Tuku Panui
  Ko te rarangi IP Release Notes nga huringa IP i roto i tetahi tukunga.

Te whakaputa i te Hoahoa Example

Tikanga

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

Exampte Ripa Hoahoa i roto i te E-Tile E-Tile 40G Itarangi Parameter Editor
Tīpakohia Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit hei whakaputa hoahoa exampmo nga taputapu Intel Stratix® 10. Tīpakohia Agilex F-series Transceiver-SoC Development Kit hei whakaputa hoahoa exampmo nga taputapu Intel Agilex™.

A pee i enei mahi ki te whakaputa i te hoahoa taputapu example me te papa whakamatautau:

1. I roto i te rorohiko Intel Quartus Prime Pro Edition, pawhiria File ➤ Ruānuku Kaupapa Hou
   ki te hanga kaupapa hou Intel Quartus Prime, ranei File ➤ Kaupapa Tuwhera hei whakatuwhera i tetahi kaupapa rorohiko Intel Quartus Prime. Ka akiaki koe e te ruānuku ki te tautuhi i te whanau taputapu me te taputapu.
   Tuhipoka: Ko te hoahoa exampKa tuhiruatia e le te kowhiringa me te taputapu i runga i te papa i whäia. Ka tohua e koe te papa whaainga mai i te tahua o te hoahoa example kōwhiringa i roto i te Exampripa Hoahoa (Step 8).
2. I roto i te Putumōhio IP, kimihia me te kowhiri i te Waahanga Iti E-Tapa 40G Ethernet Intel FPGA IP. Ka puta te matapihi Rerekē IP Hou.
3. Tauwhāitihia he ingoa taumata-runga mo to rereketanga IP ritenga. Ka tiakina e te ētita tawhā Intel Quartus Prime IP nga tautuhinga rerekētanga IP i roto i te file whakaingoatia .ip.
4. Pāwhiritia OK. Ka puta te ētita tawhā IP.
5. I te ripa IP, whakapūtāhia ngā tawhā mō tō rerekētanga matua IP.
   Tuhipoka: Ko te iti Latency E-Tile 40G Itarangi Intel FPGA IP hoahoa exampKarekau e hangai tika ana ka kore e mahi tika mena ka tohua e koe tetahi o nga tawhā e whai ake nei:
   1. Whakahohehia te tuku korero whakataki kua whakakā
   2. Kua whakaritea te torohūtanga ki te uara o te 3
   3. Whakahohea te whakaurunga TX CRC kua weto
6. I runga i te Exampripa Hoahoa, i raro i Example Hoahoa Files, whakaaheitia te kowhiringa Whakaakoranga ki te whakaputa i te pae whakamatautau, ka kowhiria te kowhiringa Synthesis hei whakaputa i te whakahiato-anake me te hoahoa taputapu o muaamples.
   Tuhipoka: I runga i te Exampte ripa Hoahoa, i raro i te Hōputu HDL Hangaia, ko Verilog HDL anake kei te waatea. Kaore tenei matua IP e tautoko i te VHDL.
7. I raro i te Kete Whakawhanake Whainga, tohua te Kete Whakawhanaketanga Whakawhanaketanga Tohu Whakawhitinga E-Tile Stratix 10 TX E-Tile ranei te Kete Whanaketanga Agilex F-series Transceiver-SoC Development Kit.
   Tuhipoka: Ko te kete whanaketanga ka tohua e koe ka tuhirua i te kowhiringa taputapu i te Hipanga
   1. Ko te taputapu whainga a Intel Stratix 10 E-tile ko 1SG280LU3F50E3VGS1.
   2. Ko te whaainga o te taputapu Intel Agilex E-tile ko AGFB014R24A2E2VR0.
8. Pāwhiritia te Hanga Exampte pātene Hoahoa. Ko te Tohu Exampka puta te matapihi Design Directory.
9. Mena kei te hiahia koe ki te whakarereke i te hoahoa exampte ara whaiaronga, ingoa ranei mai i nga taunoa kua whakaatuhia (alt_e40c3_0_example_design), tirotiro ki te ara hou ka pato i te hoahoa hou exampte ingoa whaiaronga (ample_dir>).
10. Pāwhiritia OK.

Nga korero e pa ana

• Tawhā Matua IP
  Ka whakarato i etahi atu korero mo te whakarite i to matua IP.
• Intel Stratix 10 E-Tile TX Tohu Whakawhanaketanga Taputapu Kete
• Intel Agilex F-Series FPGA Development Kit

Hoahoa Exampte Tawhā

Tawhā i roto i te Exampte Ripa Hoahoa

Tawhā	Whakaahuatanga
Tohua Hoahoa	Wātea exampte hoahoa mo nga tautuhinga tawhā IP. Ina whiriwhiria e koe he hoahoa mai i te whare pukapuka tatūkē, ka whakaatuhia e tenei mara te hoahoa kua tohua.
Example Hoahoa Files	Ko te files ki te whakaputa mo te wahanga whanaketanga rereke. •    whaihanga— whakaputa i nga mea e tika ana files mo te whakatairite i te examphoahoa. •    Te whakahiato—ka whakaputa i te whakahiato files. Whakamahia enei files ki te whakahiato i te hoahoa i roto i te rorohiko Intel Quartus Prime Pro Edition mo te whakamatautau taputapu me te mahi tātaritanga taima.
Whakaputa File Whakahōputu	Ko te whakatakotoranga o te RTL files mo te whaihanga—Verilog, VHDL ranei.
Whiriwhiria te Poari	He taputapu tautoko mo te whakatinanatanga hoahoa. Ina whiriwhiria e koe he poari whanaketanga Intel, ko te Pūrere Whāinga ko te mea e rite ana ki te taputapu kei te Kete Whakawhanaketanga. Mena kaore tenei tahua i te waatea, kaore he papa tautoko mo nga whiringa ka tohua e koe. Agilex F-series Transceiver-SoC Development Kit: Ma tenei whiringa ka taea e koe te whakamatautau i te hoahoa o muaampi runga i te kete whanaketanga Intel FPGA IP kua tohua. Ko tenei kōwhiringa ka kowhiri aunoa i te Pūrere Whāinga Ko nga waahanga mo te AGFB014R24A2E2VR0. Mēnā he kōeke pūrere rerekē tō arotake poari, ka taea e koe te huri i te pūrere ūnga.
haere tonu…

Tawhā

Whakaahuatanga

Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit: Ma tenei whiringa ka taea e koe te whakamatautau i te hoahoa o muaampi runga i te kete whanaketanga Intel FPGA IP kua tohua. Ko tenei kōwhiringa ka kowhiri aunoa i te Pūrere Whāinga o 1ST280EY2F55E2VG. Mēnā he kōeke pūrere rerekē tō arotake poari, ka taea e koe te huri i te pūrere ūnga. Karekau: Ka whakakorehia e tenei waahanga nga waahanga taputapu mo te hoahoa example.

Hanganga Whaiaronga
Te Rooputanga Iti E-Tapa 40G Itarangi IP hoahoa matua example file kei roto i nga whaiaronga nga mea hanga e whai ake nei files mo te hoahoa example.

Hanganga Whaiaronga mo te Hoahoa Hanga Example

• Te whaihanga files (whakamatautau mo te whaihanga anake) kei rotoample_dir>/example_testbench.
• Ko te whakahiato-anake exampKei roto te hoahoaample_dir>/ compilation_test_design.
• Te whirihoranga taputapu me te whakamatautau files (te hoahoa taputapu example) kei rotoample_dir>/puru_whakamatautau_hoahoa

Whaiaronga me File Whakaahuatanga

File Nga Ingoa	Whakaahuatanga
eth_ex_40g.qpf	Kaupapa Intel Quartus Prime file.
eth_ex_40g.qsf	Tautuhinga kaupapa Intel Quartus Prime file.
haere tonu…

File Nga Ingoa	Whakaahuatanga
eth_ex_40g.sdc	Synopsys* Nga Herenga Hoahoa file. Ka taea e koe te kape me te whakarereke i tenei file mo to ake hoahoa iti E-Tapa 40G Itarangi Intel FPGA IP.
eth_ex_40g.srf	Ture pehi karere kaupapa Intel Quartus Prime file.
eth_ex_40g.v	Hoahoa Verilog HDL taumata-rungaample file.
eth_ex_40g_clock.sdc	Nga herenga Hoahoa Synopsys file mo nga karaka.
noa/	Hoahoa taputapu exampte tautoko files.
hwtest/main.tcl	Matua file mo te uru atu ki te Papatohu Pūnaha.

Whakataurite i te Hoahoa Exampte Testbench
Ka taea e koe te whakahiato me te whakatairite i te hoahoa ma te whakahaere i te tuhinga whaihanga mai i te whakahau whakahau.

1. I te whakahau whakahau, hurihia te whaiaronga mahi kiample_dir>/example_testbench.
2. Whakahaerehia te tuhinga whaihanga mo te simulator tautoko e pai ana koe. Ka whakahiato me te whakahaere i te papa whakamatautau i roto i te simulator

Nga Tohutohu ki te Whakataurite i te Taumatau

Simulator	Tohutohu
TauiraSim*	I roto i te raina whakahau, pato vsim -do run_vsim.do. Ki te hiahia koe ki te whaihanga me te kore e kawe ake i te ModelSim GUI, pato vsim -c -do run_vsim.do. Tuhipoka: E kore e taea e nga simulators ModelSim-AE me ModelSim-ASE te whakataurite i tenei matua IP. Me whakamahi koe i tetahi atu tauira tauira ModelSim e tautokohia ana penei i a ModelSim SE.
VCS*	I te rarangi whakahau, patohia te sh run_vcs.sh
VCS MX	I te rarangi whakahau, pato sh run_vcsmx.sh. Whakamahia tenei tuhinga ina kei roto i te hoahoa te Verilog HDL me te System Verilog me te VHDL.
NCSim	I roto i te rarangi whakahau, patohia te sh run_ncsim.sh
Xcelium*	I roto i te rarangi whakahau, patohia te sh run_xcelium.sh

Ka mutu te whaihanga angitu me te panui e whai ake nei: Kua Paahi te Whakataunga. ranei Testbench oti. I muri i te otinga angitu, ka taea e koe te tātari i nga hua.

Te whakahiato me te whirihora i te Hoahoa Example i roto i nga taputapu
Ko te ētita tawhā matua Intel FPGA IP ka taea e koe te whakahiato me te whirihora i te hoahoa exampi runga i te kete whanaketanga whaainga

Hei whakahiato me te whirihora i tetahi hoahoa exampmo te taputapu, whai i enei mahi:

1. Whakarewahia te rorohiko Intel Quartus Prime Pro Edition ka kowhiria te Tukatuka ➤ Tīmata Whakahiato hei whakahiato i te hoahoa.
2. Whai muri i to whakaputa i tetahi ahanoa SRAM file .sof, whai i enei mahi ki te hotaka i te hoahoa taputapu exampi runga i te taputapu Intel:
   1. Tīpakohia Utauta ➤ Kaihōtaka.
   2. I roto i te Kaihōtaka, pāwhiritia te Tatūnga Pūmārō.
   3. Tīpakohia he taputapu hōtaka.
   4. Tīpakohia ka taapirihia te papa Intel TX ki to wahanga Intel Quartus Prime Pro Edition.
   5. Me whakarite kua tautuhia te Aratau ki a JTAG.
   6. Tīpakohia te taputapu Intel ka paato i te Tāpiri Pūrere. Ka whakaatuhia e te Kaihōtaka he hoahoa paraka o nga hononga i waenga i nga taputapu i runga i to papa.
   7. I te rarangi me to .sof, tirohia te pouaka mo te .sof.
   8. Whakakāhia te kōwhiringa Papatono / Whirihora mo te .sof.
   9. Pāwhiritia Tīmata.

Nga korero e pa ana

• Whakahiato Whakanuia mo te Hoahoa Arataki me te Hoahoa-Tiopu
• Papatonotanga Intel FPGA Pūrere

Te Huri i te Pūrere Ūnga ki te Hoahoa Pūmārō Example
Mena kua tohua e koe a Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit hei taputapu e whaaia ana e koe, ka hangaia e te Waahanga Iti E-Tile 40G Ethernet Intel FPGA IP matua he taputapu o mua.ampte hoahoa mo te taputapu whaainga 1ST280EY2F55E2VG. Mena kua tohua e koe a Agilex F-series Transceiver-SoC Development Kit hei taputapu e whaaia ana e koe, ko te E-Tapa iti 40G Ethernet Intel FPGA IP matua ka whakaputa i tetahi taputapu o mua.ampte hoahoa mo te taputapu whaainga AGFB014R24A2E2VR0. He rereke pea te taputapu kua tohua mai i te taputapu kei runga i to kete whanaketanga. Ki te huri i te pūrere ūnga i roto i to koutou hoahoa taputapu exampe, whai i enei kaupae:

1. Whakarewahia te rorohiko Intel Quartus Prime Pro Edition ka whakatuwhera i te kaupapa whakamatautau taputapu file /hardware_test_design/eth_ex_40g.qpf.
2. I te tahua Taumahi, pāwhiritia te Pūrere. Ka puta te pouaka korero Pūrere.
3. I roto i te pouaka korero Pūrere, tīpakohia he ripanga taputapu e hāngai ana ki te E-tile e rite ana ki te nama waahanga taputapu kei runga i to kete whanaketanga. Tirohia te hononga kete whanaketanga i runga i te Intel webpae mo etahi atu korero.
4. Ka puta he tohu ina tohua e koe he taputapu, penei i te ahua i raro nei. Tīpakohia Kāo hei pupuri i ngā taumahi titi i hangaia me ngā taumahi I/O.
   Intel Quartus Prime Prompt mo te Whiriwhiringa Pūrere
5. Mahia te whakahiato katoa o to hoahoa.

Ka taea e koe te whakamatautau i te hoahoa i runga i to taputapu.

Nga korero e pa ana

• Intel Stratix 10 E-Tile TX Tohu Whakawhanaketanga Taputapu Kete
• Intel Agilex F-Series FPGA Development Kit

Te Whakamatau i te Taapapa iti E-Tapa 40G Itarangi Intel FPGA IP Hoahoa i roto i nga taputapu
Whai muri i to whakahiato i te hoahoa matua E-Tile 40G Itarangi Intel FPGA IP exampme te whirihora i runga i to taputapu Intel, ka taea e koe te whakamahi i te Papatohu Pūnaha ki te hotaka i te matua IP me ona rehita matua PHY IP taketake. Hei whakakā i te Pūnaha Papatohu me te whakamatautau i te hoahoa taputapu exampe, whai i enei kaupae:

1. I roto i te rorohiko Intel Quartus Prime Pro Edition, tohua Utauta ➤ Utauta Patuiro Pūnaha ➤ Papatohu Pūnaha hei whakarewa i te papatohu punaha.
2. I te pihanga Tcl Console, patohia te cd hwtest hei huri i te whaiaronga ki /hardware_test_design/hwtest.
3. Patohia te puna main.tcl hei whakatuwhera hononga ki te JTAG rangatira.

Hoahoa taapiri exampKei te waatea nga whakahau ki te whakarite i te kaupapa IP:

• chkphy_status: Ka whakaatu i nga iarere karaka me te mana maukati PHY.
• chkmac_stats: Ka whakaatu i nga uara i roto i nga tatauranga tatauranga MAC.
• clear_all_stats: Ka whakawātea i ngā porotiti tatauranga matua IP.
• start_pkt_gen: Tīmatahia te kaihanga pākete.
• stop_pkt_gen: Ka whakamutua te kaihanga kete.
• sys_reset_digital_analog: Tautuhi ano o te punaha.
• koropiko_i: Ka whakahurihia te hurihanga rangatū o roto
• takahuri: Whakawetohia te hurihanga rangatū o roto.
• reg_panui : Whakahokia te uara rehita matua IP i .
• reg_tuhi : Ka tuhi ki te rehita matua IP i te wahitau .

A pee i te tukanga whakamatautau i te waahanga Whakamātautau Hardware o te hoahoa exampme te titiro ki nga hua whakamatautau i roto i te Papatohu Pūnaha.

Nga korero e pa ana
Te Tatari me te Patuiro Hoahoa me te Papatohu Pūnaha

Hoahoa Example Whakaahuatanga

Ko te hoahoa E-taipa 40G Ethernet exampe whakaatu ana i nga mahi o te E-Tile Low Latency 40G Ethernet Intel FPGA IP matua, me te E-tile based transceiver atanga e rite ana ki te IEEE 802.3ba paerewa CAUI-4. Ka taea e koe te whakaputa i te hoahoa mai i te Exampte Ripa Hoahoa i roto i te E-Tapa iti 40G Itarangi Intel FPGA IP ētita tawhā.
Hei whakaputa i te hoahoa exampNa, me whakarite e koe nga uara tawhā mo te rereketanga matua IP e hiahia ana koe ki te whakaputa i to hua mutunga. Te whakaputa i te hoahoa exampKa hangaia e ia he kape o te IP matua; te papa whakamatautau me te hoahoa taputapu exampMe whakamahi tenei rereke hei DUT. Ki te kore koe e tautuhi i nga uara tawhā mo te DUT kia rite ki nga uara tawhā i to hua mutunga, te hoahoa exampka whakaputa koe e kore e whakamahi i te rereketanga matua IP e hiahia ana koe.

Tuhipoka:
Ka whakaatuhia e te testbench he whakamatautau taketake o te matua IP. Ehara i te mea hei whakakapi mo te taiao manatoko katoa. Me kaha ake koe ki te whakamana i a koe ake E-Tapa iti 40G Itarangi Intel FPGA IP hoahoa i roto i te whaihanga me te taputapu.

Ngā āhuatanga

• E tautoko ana i te 40G Ethernet MAC/PCS IP matua mo te E-tile transceiver ma te whakamahi i te taputapu Intel Stratix 10, Intel Agilex ranei.
• Ka tautoko i te whakangungu whakawhiti korero me te hononga hono.
• Ka whakaputa hoahoa exampme nga tohu kaute MAC.
• Ka whakarato i te papamahi whakamatautau me te tuhinga whaihanga.

Nga Whakaritenga Pumau me nga Pūmanawa
Hei whakamatautau i te exampte hoahoa, whakamahia nga taputapu me nga rorohiko e whai ake nei:

• Pūmanawa Intel Quartus Prime Pro Edition
• Papatohu Pūnaha
• ModelSim, VCS, VCS MX, NCSim, Xcelium Simulator ranei
• Intel Stratix 10 TX E-Tile Transceiver Waitohu Whakawhanake Taputapu Kete Whakawhanaketanga Taputapu ranei Intel Agilex F-series Transceiver-SoC Development Kit

Whakaahuatanga Mahi
Ko tenei waahanga e whakaatu ana i te 40G Ethernet MAC/PCS IP matua ma te whakamahi i te taputapu Intel i roto i te whakawhiti whakawhiti E-tile. I roto i te ahunga tuku, ka whakaae te MAC ki nga papa a te kiritaki me te whakauru i te aputa i waenga-packet (IPG), te kupu whakataki, te tiimatanga o te whakawehe anga (SFD), te padding, me nga paraka CRC i mua i te tuku ki te PHY. Ka whakawaeheretia e te PHY te anga MAC e hiahiatia ana mo te tuku pono i runga i te papapāho ki te pito mamao. I te ahunga whiwhi, ka tukuna e te PHY nga papa ki te MAC. Ka whakaaehia e te MAC nga papa mai i te PHY, ka mahi i nga arowhai, ka tihorea te CRC, te preamble, me te SFD, ka tukuna te toenga o te anga ki te kiritaki.

whaihanga

Ka tukuna e te testbench nga waka ma te IP matua, te whakamahi i te taha tuku me te whiwhi taha o te matua IP.

Roopu iti E-Tapa 40G Itarangi Hoahoa Exampte Hoahoa Poraka

Ko te hoahoa whaihanga exampte whakamātautau taumata-runga file ko basic_avl_tb_top.sv. Tenei file he tohutoro karaka clk_ref o 156.25 Mhz ki te PHY. Kei roto he mahi ki te tuku me te tango i nga paatete 10.

Te Rooputanga Iti E-Tapa 40G Itarangi Matua Whakamatau File Whakaahuatanga

File Nga Ingoa	Whakaahuatanga
Testbench me te whaihanga Files
basic_avl_tb_top.sv	Te pae whakamatautau taumata-runga file. Ka tukuna e te papa whakamatautau te DUT me te whakahaere i nga mahi a Verilog HDL hei whakaputa me te whakaae i nga paanui.
basic_avl_tb_top_nc.sv	Te pae whakamatautau taumata-runga file he hototahi ki te simulator NCSim.
basic_avl_tb_top_msim.sv	Te pae whakamatautau taumata-runga file he hototahi ki te simulator ModelSim.
Nga Tuhituhi Whakamatau
run_vsim.do	Ko te Whakairoiro Tauira* ModelSim tuhi hei whakahaere i te papa whakamatautau.
run_vcs.sh	Ko te tuhinga Synopsys VCS hei whakahaere i te papa whakamatautau.
haere tonu…

File Nga Ingoa	Whakaahuatanga
run_vcsmx.sh	Ko te tuhinga Synopsys VCS MX (he whakakotahi i te Verilog HDL me te System Verilog me te VHDL) hei whakahaere i te papa whakamatautau.
run_ncsim.sh	Ko te tuhinga a Cadence NCSim hei whakahaere i te papa whakamatautau.
run_xcelium.sh	Ko te tuhinga a Cadence Xcelium hei whakahaere i te papa whakamatautau.

Ko te oma whakamatautau angitu ka whakaatu i te putanga e whakau ana i te whanonga e whai ake nei:

1. E tatari ana kia tau te karaka RX
2. Tā te mana PHY
3. Te tuku 10 nga paatete
4. Ka whiwhi 10 nga paatete
5. Kei te whakaatu "Kua oti te Whakamatau."

Ko nga s e whai ake neiampKo te putanga e whakaatu ana i te oma whakamatautau whaihanga angitu:

• #Tatari ana mo te whakatikatika RX
• #RX te papamahi kua maukati
• #RX tirohanga ara kua maukati
• #TX kua whakahohea
• #**Tuku ana i te Paati 1…
• #**Tuku ana i te Paati 2…
• #**Tuku ana i te Paati 3…
• #**Tuku ana i te Paati 4…
• #**Tuku ana i te Paati 5…
• #**Tuku ana i te Paati 6…
• #**Tuku ana i te Paati 7…
• #**Kua Putea 1…
• #**Tuku ana i te Paati 8…
• #**Kua Putea 2…
• #**Tuku ana i te Paati 9…
• #**Kua Putea 3…
• #**Tuku ana i te Paati 10…
• #**Kua Putea 4…
• #**Kua Putea 5…
• #**Kua Putea 6…
• #**Kua Putea 7…
• #**Kua Putea 8…
• #**Kua Putea 9…
• #**Kua Putea 10…

Nga korero e pa ana
Whakataurite i te Hoahoa Example Testbench i te wharangi 7

Whakamātautau Pūmārō
I roto i te hoahoa taputapu exampNa, ka taea e koe te whakarite i te IP matua i roto i te aratau loopback rangatū o roto, me te whakaputa waka i runga i te taha tuku e koropiko hoki i roto i te taha whiwhi.

Roopu iti E-Tapa 40G Itarangi IP Hoahoa Pūmārō Example Hoahoa Poraka Taumata teitei

Ko te Taapapa Iti E-Tapa 40G Itarangi hoahoa taputapu exampKei roto i nga waahanga e whai ake nei:

• Terenga iti E-Tapa 40G Itarangi Intel FPGA IP matua.
• Ko te arorau a te kiritaki e whakarite ana i te hotaka o te IP matua, me te whakaputa paatete me te tirotiro.
• IOPLL ki te whakaputa karaka 100 MHz mai i te karaka whakauru 50 MHz ki te hoahoa taputapu o muaample.
• JTAG kaiwhakahaere e korero ana ki te Intel System Console. Ka whakawhitiwhiti korero koe me te whakaaro a te kiritaki ma te Papatohu Pūnaha.

A pee i te tikanga i te hono korero e pa ana ki te whakamatau i te hoahoa example i roto i te taputapu kua tohua.

Nga korero e pa ana

• Te Whakamatau i te Tapa E-Tiki 40G Itarangi Intel FPGA IP Hoahoa i roto i nga taputapu i te wharangi 9
• Te Tatari me te Patuiro Hoahoa me te Papatohu Pūnaha

Whakamātautau Loopback Roto
Whakahaerehia enei mahi hei mahi i te whakamatautau whakamuri o roto:

1. Tautuhi ano i te punaha.
   sys_reset_digital_analog
2. Whakaatuhia te auau karaka me te mana PHY.
   chkphy_status
3. Whakakāngia te whakamātautau whakamuri o roto.
   koropiko_i
4. Whakaatuhia te auau karaka me te mana PHY. Kua whakaritea te rx_clk ki te 312.5 MHz me te
   rx_pcs_ready kua whakaritea ki te 1.
   chkphy_status
5. Tīmatahia te kaihanga pākete.
   start_pkt_gen
6. Whakamutua te kaihanga putea.
   stop_pkt_gen
7. Review te maha o nga paatete kua tukuna me te whiwhi.
   chkmac_stats
8. Whakamutua te whakamatautau whakamuri o roto.
   takahuri

Whakamātautau Loopback o waho
Whakahaerehia enei mahi hei mahi i te whakamatautau whakamuri o waho:

1. Tautuhi ano i te punaha.
   sys_reset_digital_analog
2. Whakaatuhia te auau karaka me te mana PHY. Kua whakaritea te rx_clk ki te 312.5 MHz me te
   rx_pcs_ready is set to 1. chkphy_status
3. Tīmatahia te kaihanga pākete.
   start_pkt_gen
4. Whakamutua te kaihanga putea.
   stop_pkt_gen
5. Review te maha o nga paatete kua tukuna me te whiwhi.
   chkmac_stats

Roopu iti E-Tapa 40G Itarangi Hoahoa Example Rehita

Terenga iti E-Tapa 40G Itarangi Hoahoa Pūmārō Example Mahere Rehita
Ka whakarārangihia nga awhe rehita kua mapi mahara mo te hoahoa taputapu example. Ka uru koe ki enei rehita me nga mahi reg_read me reg_write i roto i te Papatohu Pūnaha.

Kupu Whangai	Momo Rēhita
0x300-0x3FF	Rehita PHY
0x400-0x4FF	Rehita TX MAC
0x500-0x5FF	RX MAC rehita
0x800-0x8FF	Rehita Kaitatau Tatauranga - Te ahunga TX
0x900-0x9FF	Rehita Kaitatau Tatauranga – RX aronga
0x1000-1016	Ko nga rehitatanga o te Kiritaki Paetahi

Nga Rehita Kiritaki Packet
Ka taea e koe te whakarite i te hoahoa taputapu Itarangi E-Tile 40G Ethernet exampma te whakahoahoa i nga rehita o nga kaihoko.

Tuhinga	Ingoa	Bit	Whakaahuatanga	HW Tautuhi Uara	Urunga
0x1008	Whakaritea Rahi Pakete	[29:0]	Tauwhāitihia te rahi o te pākete tuku i roto i nga paita. Ko enei moka he herenga ki te rehita PKT_GEN_TX_CTRL. • Moka [29:16]: Tauwhāitihia te tepe o runga o te rahi o te kete i roto i nga paita. E tika ana tenei ki te aratau taapiri. • Moka [13:0]: - Mo te aratau pumau, ko enei paraka e tohu te rahi o te paatete tuku i roto i nga paita. — Mo te aratau taapiri, ko enei moka e tohu ana i nga paita taapiri mo tetahi paatete.	0x25800040	RW
0x1009	Mana Tau Pakete	[31:0]	Tauwhāitihia te maha o ngā pākete hei tuku mai i te kaihanga pākete.	0xA	RW
0x1010	PKT_GEN_TX_C TRL	[7:0]	• Moka [0]: Kua rahuitia. • Moka [1]: Moka whakawetohia te kaihanga putea. Tautuhia tenei moka ki te uara o te 1 hei whakaweto i te kaihanga pakete, ka tautuhi ano ki te uara o te 0 hei whakakorikori i te kaihanga kete. • Moka [2]: Kua rahuitia. • Moka [3]: He 1 te uara ki te mea kei roto te kaupapa IP kei te aratau whakahuri MAC; he 0 te uara ki te whakamahia e te kaihoko paatete te kaihanga paatete.	0x6	RW
haere tonu…

Tuhinga	Ingoa	Bit	Whakaahuatanga	HW Tautuhi Uara	Urunga
			• Moka [5:4]: — 00: Aratau tupurangi — 01: Aratau u — 10: Aratau taapiri • Moka [6]: Tautuhia tenei moka ki te 1 hei whakamahi i te rehita 0x1009 ki te whakaweto i te kaihanga kete i runga i te maha o nga paatete hei tuku. Ki te kore, ka whakamahia te moka [1] o te rehita PKT_GEN_TX_CTRL hei whakaweto i te kaihanga kete. • Moka [7]: — 1: Mo te tuku kaore he mokowhiti i waenga i nga paatete. — 0: Mo te tuku me te aputa matapōkere i waenga i ngā pākete.
0x1011	Wāhitau ūnga iti 32 moka	[31:0]	Wāhitau ūnga (32 bits raro)	0x56780ADD	RW
0x1012	Wāhitau ūnga o runga 16 moka	[15:0]	Wāhitau ūnga (16 moka runga ake)	0x1234	RW
0x1013	Wāhitau mātāpuna 32 paraka raro	[31:0]	Wāhitau puna (32 moka iti iho)	0x43210ADD	RW
0x1014	Wāhitau puna o runga 16 moka	[15:0]	Wāhitau puna (16 moka runga ake)	0x8765	RW
0x1016	PKT_CL_LOOPB ACK_RESET	[0]	MAC loopback tautuhi. Tautuhia ki te uara o te 1 hei tautuhi i te hoahoa exampte MAC loopback.	1'b0	RW

Nga korero e pa ana
E-Tapa iti 40G Ethernet Mana me nga Whakaahuatanga Rēhita Tūnga E whakaatu ana i nga rehita matua IP Latency E-Tile 40G Ethernet IP.

Hoahoa Example Tohu Atanga
Ko te papa whakamatautau E-Tapa iti 40G Ethernet kei roto i a koe ano, kaore koe e tono kia peia etahi tohu whakauru.

Terenga iti E-Tapa 40G Itarangi Hoahoa Pūmārō Example Tohu Atanga

Waitohu	Te aronga	Nga korero
clk50	Whakauru	Ko tenei karaka ka peia e te oscillator poari. • Peia i te 50 MHz i runga i te papa Intel Stratix 10. • Peia i te 100 MHz i runga i te papa Intel Agilex. Ko te hoahoa taputapu exampKa arataki i tenei karaka ki te whakaurunga o te IOPLL i runga i te taputapu me te whirihora i te IOPLL kia peia he karaka 100 MHz ki roto.
clk_ref	Whakauru	Peia i te 156.25 MHz.
haere tonu…

Waitohu	Te aronga	Nga korero
cpu_resetn	Whakauru	Ka tautuhi ano i te matua IP. Hohe iti. Ka peia te tautuhi pakeke csr_reset_n ki te matua IP.
tx_rangatū[3:0]	Putanga	Whakaputa PHY raraunga rangatū.
rx_rangatū[3:0]	Whakauru	Kaituku PHY whakauru raraunga rangatū.
Kaiwhakamahi_arata[7:0]	Putanga	Tohu tūnga. Ko te hoahoa taputapu exampKa honoa enei moka ki te tarai i nga rama ki runga i te papa i tohua. Ko nga moka takitahi e whakaatu ana i nga uara tohu me te whanonga karaka e whai ake nei: • [0]: Tohu tautuhi matua ki te matua IP • [1]: Putanga wehea o clk_ref • [2]: Putanga wehea o clk50 • [3]: Putanga wehea o te karaka mana 100 MHz • [4]: ​​tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready

Nga korero e pa ana
Nga Atanga me nga Whakaaturanga Waitohu Ka whakarato i nga whakaahuatanga mo nga tohu matua o te E-Tapa iti 40G Ethernet IP me nga atanga no ratou.

Rorohiko iti E-Tapa 40G Itarangi Intel FPGA IP Archives
Ki te kore e whakarārangitia he putanga matua IP, ka pa te aratohu kaiwhakamahi mo te putanga matua IP o mua.

Intel Quartus Prime Putanga	Putanga Matua IP	Aratohu Kaiwhakamahi
20.1	19.1.0	Roopu iti E-Tapa 40G Itarangi Hoahoa Exampte Aratohu Kaiwhakamahi

Tuhinga o mua Tuhinga mo te Roopu iti E-tile 40G Itarangi Hoahoa Exampte Aratohu Kaiwhakamahi

Putanga Tuhinga	Intel Quartus Prime Putanga	Putanga IP	Huringa
2020.06.22	20.2	20.0.0	He tautoko taputapu taapiri mo nga taputapu Intel Agilex.
2020.04.13	20.1	19.1.0	Tukunga Tuatahi.

Intel Corporation. Katoa nga mana. Ko Intel, ko te tohu Intel, me etahi atu tohu Intel he tohu hokohoko na Intel Corporation me ona apiti. Ka whakamanahia e Intel te mahinga o ana hua FPGA me nga hua semiconductor ki nga whakaritenga o naianei i runga i te raihana paerewa a Intel, engari ka whai mana ki te whakarereke i nga hua me nga ratonga i nga wa katoa kaore he panui. Karekau a Intel he kawenga, he taunahatanga ranei i puta mai i te tono, i te whakamahinga ranei o nga korero, hua, ratonga ranei e whakaahuatia ana i konei engari ko nga mea i tino whakaaehia a Intel. Ka tohutohuhia nga kaihoko a Intel ki te tiki i te putanga hou o nga whakaritenga taputapu i mua i te whakawhirinaki ki nga korero kua whakaputaina me i mua i te tuku ota mo nga hua, ratonga ranei. Ko etahi atu ingoa me etahi atu tohu ka kiia he taonga na etahi atu.

Tuhinga / Rauemi

intel Tere iti E-Tapa 40G Itarangi Intel FPGA IP Hoahoa Example [pdf] Aratohu Kaiwhakamahi Terenga iti E-Tapa 40G Itarangi Intel FPGA IP Hoahoa Example, Latency Iti, E-Tile 40G Itarangi Intel FPGA IP Hoahoa Example, Intel FPGA IP Hoahoa Example, IP Hoahoa Example

Tohutoro

• Pukapuka Kaiwhakamahi